diff options
| author | Youness Alaoui <youness.alaoui@puri.sm> | 2018-03-13 16:53:30 -0400 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-03-26 10:25:41 +0000 |
| commit | 6aa28d93b354845e96c7154b1670864fa48ac16a (patch) | |
| tree | 69840edbcd4924f8dc73e0c4a19ef063727372cb | |
| parent | 7a2cf650326f115215cfbd921514453beeb26c6a (diff) | |
| download | coreboot-6aa28d93b354845e96c7154b1670864fa48ac16a.tar.xz | |
purism/librem13v1, librem13v2, liberm15v3: Fix EC LPC I/O port
The LPC I/O ports for EC communication were not set properly,
causing ectool to fail to read the Index I/O from the EC.
The EC Index I/O is on port 0x380 and the LPC I/O port needs to be
decoded by the PCI device for it to be accessible.
Correct the value for the Librem 13v1, 13v2 and 15v3.
Change-Id: Ide1d158340eadfabbce5f70ceccddfabb4db188a
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/25328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
3 files changed, 10 insertions, 6 deletions
diff --git a/src/mainboard/purism/librem13v1/devicetree.cb b/src/mainboard/purism/librem13v1/devicetree.cb index ba38070a55..c916e9a9a4 100644 --- a/src/mainboard/purism/librem13v1/devicetree.cb +++ b/src/mainboard/purism/librem13v1/devicetree.cb @@ -18,6 +18,10 @@ chip soc/intel/broadwell register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms + # EC host command ranges are in 0x380-0x383 & 0x80-0x8f + register "gen1_dec" = "0x00000381" + register "gen2_dec" = "0x000c0081" + # Port 0 is HDD # Port 3 is M.2 NGFF register "sata_port_map" = "0x9" diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb index 1fc19a5675..50e484b0df 100644 --- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb @@ -15,9 +15,9 @@ chip soc/intel/skylake register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + # EC host command ranges are in 0x380-0x383 & 0x80-0x8f + register "gen1_dec" = "0x00000381" + register "gen2_dec" = "0x000c0081" # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb index 647f054f74..a52e4b7e3f 100644 --- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb @@ -15,9 +15,9 @@ chip soc/intel/skylake register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" + # EC host command ranges are in 0x380-0x383 & 0x80-0x8f + register "gen1_dec" = "0x00000381" + register "gen2_dec" = "0x000c0081" # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" |