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authorFelix Held <felix-coreboot@felixheld.de>2019-12-27 18:00:53 +0100
committerFelix Held <felix-coreboot@felixheld.de>2019-12-30 02:57:37 +0000
commit734c999637357ef62c305c8dfd559def176b00ff (patch)
treeba399550dc45d455d4c4730ccf2733ec2711e17b
parent35103fd961bb5fed318dd3b842582648541586e3 (diff)
downloadcoreboot-734c999637357ef62c305c8dfd559def176b00ff.tar.xz
ibase/mb899: use common winbond/nuvoton HWM bank select function
Change-Id: I7f159074c25a0fdfe2ee15024c1ed6c062ce75d5 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
-rw-r--r--src/mainboard/ibase/mb899/Kconfig1
-rw-r--r--src/mainboard/ibase/mb899/superio_hwm.c7
2 files changed, 5 insertions, 3 deletions
diff --git a/src/mainboard/ibase/mb899/Kconfig b/src/mainboard/ibase/mb899/Kconfig
index d93121dc2d..b3ffd2bee5 100644
--- a/src/mainboard/ibase/mb899/Kconfig
+++ b/src/mainboard/ibase/mb899/Kconfig
@@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS
select CHECK_SLFRCS_ON_RESUME
select SOUTHBRIDGE_INTEL_I82801GX
select SUPERIO_WINBOND_W83627EHG
+ select SUPERIO_NUVOTON_COMMON_HWM # Nuvoton is a Winbond spin-off
select HAVE_ACPI_TABLES
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
diff --git a/src/mainboard/ibase/mb899/superio_hwm.c b/src/mainboard/ibase/mb899/superio_hwm.c
index aa88cc76ed..175c9a0d5a 100644
--- a/src/mainboard/ibase/mb899/superio_hwm.c
+++ b/src/mainboard/ibase/mb899/superio_hwm.c
@@ -19,6 +19,7 @@
#include <device/device.h>
#include <pc80/mc146818rtc.h>
#include <superio/hwm5_conf.h>
+#include <superio/nuvoton/common/hwm.h>
#include "superio_hwm.h"
@@ -82,16 +83,16 @@ void hwm_setup(void)
// pnp_write_hwm5_index(HWM_BASE, 0x31, 0x20); // AVCC high limit
// pnp_write_hwm5_index(HWM_BASE, 0x34, 0x06); // VIN2 low limit
- pnp_write_hwm5_index(HWM_BASE, 0x4e, 0);
+ nuvoton_hwm_select_bank(HWM_BASE, 0);
pnp_write_hwm5_index(HWM_BASE, 0x59, 0x20); // Diode Selection
pnp_write_hwm5_index(HWM_BASE, 0x5d, 0x0f); // All Sensors Diode, not Thermistor
- pnp_write_hwm5_index(HWM_BASE, 0x4e, 4);
+ nuvoton_hwm_select_bank(HWM_BASE, 4);
pnp_write_hwm5_index(HWM_BASE, 0x54, 0xf1); // SYSTIN temperature offset
pnp_write_hwm5_index(HWM_BASE, 0x55, 0x19); // CPUTIN temperature offset
pnp_write_hwm5_index(HWM_BASE, 0x56, 0xfc); // AUXTIN temperature offset
- pnp_write_hwm5_index(HWM_BASE, 0x4e, 0x80); // Default
+ nuvoton_hwm_select_bank(HWM_BASE, 0x80); // Default
u8 fan_config = 0;
// 00 FANOUT is Manual Mode