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| author | Patrick Rudolph <siro@das-labor.org> | 2017-05-03 18:38:21 +0200 |
|---|---|---|
| committer | Patrick Rudolph <siro@das-labor.org> | 2017-05-21 16:38:20 +0200 |
| commit | 7565cf1a49bf9688e636e1ebc6a4cb8e1e567e1b (patch) | |
| tree | bf8543e00c5979ff62739ffe1dc903c775b780c4 | |
| parent | cfa2eaa4cc268e9ed23c5a8635bb8125d985c94e (diff) | |
| download | coreboot-7565cf1a49bf9688e636e1ebc6a4cb8e1e567e1b.tar.xz | |
sb/intel/bd82x6x/finalize: Lock ETR3 CF9GR
Lock CF9GR as documented in "100-series-chipset-datasheet-vol-2.pdf"
Change-Id: I2cb30267a6342db1f3b11715034219ffb18ca678
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
| -rw-r--r-- | src/southbridge/intel/bd82x6x/finalize.c | 3 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 1 |
2 files changed, 4 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c index 4e08fc68d3..9c453e4611 100644 --- a/src/southbridge/intel/bd82x6x/finalize.c +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -65,6 +65,9 @@ void intel_pch_finalize_smm(void) /* GEN_PMCON Lock */ pci_or_config8(PCH_LPC_DEV, GEN_PMCON_LOCK, (1 << 1) | (1 << 2)); + /* ETR3: CF9GR Lockdown */ + pci_update_config32(PCH_LPC_DEV, ETR3, ~ETR3_CF9GR, ETR3_CF9LOCK); + /* R/WO registers */ RCBA32(0x21a4) = RCBA32(0x21a4); pci_write_config32(PCI_DEV(0, 27, 0), 0x74, diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index da1f901f5e..f8131da062 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -144,6 +144,7 @@ early_usb_init (const struct southbridge_usb_port *portmap); #define ETR3 0xac #define ETR3_CWORWRE (1 << 18) #define ETR3_CF9GR (1 << 20) +#define ETR3_CF9LOCK (1 << 31) /* GEN_PMCON_3 bits */ #define RTC_BATTERY_DEAD (1 << 2) |