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authorArthur Heymans <arthur@aheymans.xyz>2018-06-16 20:01:47 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2018-06-27 11:48:53 +0000
commit7875dbd9812e2359de2c5aed7754703138878466 (patch)
tree9b49b722d780bd2707e4764b6a85239e5cd916de
parentce9f422b512c376ba0eeec41db92d9a87155105a (diff)
downloadcoreboot-7875dbd9812e2359de2c5aed7754703138878466.tar.xz
cpu/intel/p4-netburst: skip caching rom on model_fxx
An unidentified combination of speculative reads and branch predictions inside WRPROT-cacheable memory can cause invalidation of cachelines and loss of stack on models based on NetBurst microarchitecture. Therefore disable WRPROT region entirely for all family F models. As an extreme example, just changing the location of a constant string passed to printk() has been witnessed to make a the boot fail early on in romstage. Change-Id: I1df84ad55e2d8d6d4e8dca10125131b5f525f0d7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
-rw-r--r--src/cpu/intel/car/p4-netburst/cache_as_ram.S14
1 files changed, 14 insertions, 0 deletions
diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
index 63ee7236ea..95ecba96bd 100644
--- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S
+++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S
@@ -315,6 +315,18 @@ no_msr_11e:
orl $CR0_CacheDisable, %eax
movl %eax, %cr0
+ /*
+ * An unidentified combination of speculative reads and branch
+ * predictions inside WRPROT-cacheable memory can cause invalidation
+ * of cachelines and loss of stack on models based on NetBurst
+ * microarchitecture. Therefore disable WRPROT region entirely for
+ * all family F models.
+ */
+ movl $1, %eax
+ cpuid
+ cmp $0xf, %ah
+ je skip_cache_rom
+
/* Enable cache for our code in Flash because we do XIP here */
movl $MTRR_PHYS_BASE(1), %ecx
xorl %edx, %edx
@@ -332,6 +344,8 @@ no_msr_11e:
movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
wrmsr
+skip_cache_rom:
+
post_code(0x2e)
/* Enable cache. */
movl %cr0, %eax