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authorTimothy Pearson <tpearson@raptorengineeringinc.com>2015-08-28 19:52:05 -0500
committerMartin Roth <martinroth@google.com>2015-12-18 19:47:01 +0100
commit7b22d84d55386ee422fa77c1d8bce9dddeaaa231 (patch)
tree7c1afd131b1c3a504bae653cffb3e87d5062dac0
parent5a3f1e54d55b416361d486d3b9136c65b6847242 (diff)
downloadcoreboot-7b22d84d55386ee422fa77c1d8bce9dddeaaa231.tar.xz
drivers/pc80: Add optional spinlock for nvram CBFS access
When enabling the IOMMU on certain systems dmesg is spammed with I/O page faults like the following: AMD-Vi: Event logged [IO_PAGE_FAULT device=00:14.0 domain=0x000a address=0x000000fdf9103300 flags=0x0030] Decoding the faulting address: 0x000000fdf9103300 fdf91x Hypertransport system management region 33 SysMgtCmd (System Management Command) = 0x33 3 Base Command Type = 0x3: STPCLK (Stop Clock request) 3 SMAF (System Management Action Field) = [3:1] = 0x1 1 Signal State Bit Map = [0] = 0x1 Therefore, the error appears to be triggered by an upstream C1E request. This was eventually traced to concurrent access to the SP5100's SPI Flash controller by multiple APs during startup. Calls to the nvram read functions get_option and read_option call CBFS functions, which in turn make near-simultaneous requests to the SPI Flash controller, thus placing the SP5100 in an invalid state. This limitation is not documented in any public AMD errata, and was only discovered through considerable debugging effort. Change-Id: I4e61b1ab767b1b7958ac7c1cf20eee41d2261bef Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12061 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
-rw-r--r--src/Kconfig8
-rw-r--r--src/arch/x86/include/arch/smp/spinlock.h4
-rw-r--r--src/cpu/amd/car/post_cache_as_ram.c3
-rw-r--r--src/drivers/pc80/mc146818rtc.c25
4 files changed, 37 insertions, 3 deletions
diff --git a/src/Kconfig b/src/Kconfig
index 6fbc1f0b10..38cf855cc8 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -480,6 +480,14 @@ config HAVE_ROMSTAGE_CONSOLE_SPINLOCK
bool
default n
+config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK
+ bool
+ default n
+ help
+ This should be enabled on certain plaforms, such as the AMD
+ SR565x, that cannot handle concurrent CBFS accesses from
+ multiple APs during early startup.
+
config HAVE_MONOTONIC_TIMER
def_bool n
help
diff --git a/src/arch/x86/include/arch/smp/spinlock.h b/src/arch/x86/include/arch/smp/spinlock.h
index 74e532c68a..057d9e3f8f 100644
--- a/src/arch/x86/include/arch/smp/spinlock.h
+++ b/src/arch/x86/include/arch/smp/spinlock.h
@@ -1,7 +1,7 @@
#ifndef ARCH_SMP_SPINLOCK_H
#define ARCH_SMP_SPINLOCK_H
-#if !defined(__PRE_RAM__) || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK)
+#if !defined(__PRE_RAM__) || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK) || IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK)
/*
* Your basic SMP spinlocks, allowing only a single CPU anywhere
@@ -14,6 +14,8 @@ typedef struct {
#ifdef __PRE_RAM__
spinlock_t *romstage_console_lock(void);
void initialize_romstage_console_lock(void);
+spinlock_t* romstage_nvram_cbfs_lock(void);
+void initialize_romstage_nvram_cbfs_lock(void);
#endif
#define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 }
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index 8c5757e209..435fdcb588 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -79,6 +79,9 @@ static void prepare_ramstage_region(void *resume_backup_memory)
#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK)
initialize_romstage_console_lock();
#endif
+#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK)
+ initialize_romstage_nvram_cbfs_lock();
+#endif
print_car_debug(" Done\n");
}
diff --git a/src/drivers/pc80/mc146818rtc.c b/src/drivers/pc80/mc146818rtc.c
index 0c95265c61..6c39f812b9 100644
--- a/src/drivers/pc80/mc146818rtc.c
+++ b/src/drivers/pc80/mc146818rtc.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright 2014 The Chromium OS Authors. All rights reserved.
+ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -33,6 +34,16 @@
#define LB_CKS_LOC 0
#endif
+#include <smp/spinlock.h>
+
+#if (defined(__PRE_RAM__) && \
+IS_ENABLED(CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK))
+ #define LOCK_NVRAM_CBFS_SPINLOCK spin_lock(romstage_nvram_cbfs_lock());
+ #define UNLOCK_NVRAM_CBFS_SPINLOCK spin_unlock(romstage_nvram_cbfs_lock());
+#else
+ #define LOCK_NVRAM_CBFS_SPINLOCK
+ #define UNLOCK_NVRAM_CBFS_SPINLOCK
+#endif
static void cmos_reset_date(void)
{
@@ -204,6 +215,8 @@ enum cb_err get_option(void *dest, const char *name)
if (!IS_ENABLED(CONFIG_USE_OPTION_TABLE))
return CB_CMOS_OTABLE_DISABLED;
+ LOCK_NVRAM_CBFS_SPINLOCK
+
/* Figure out how long name is */
namelen = strnlen(name, CMOS_MAX_NAME_LENGTH);
@@ -213,6 +226,8 @@ enum cb_err get_option(void *dest, const char *name)
if (!ct) {
printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. "
"Options are disabled\n");
+
+ UNLOCK_NVRAM_CBFS_SPINLOCK
return CB_CMOS_LAYOUT_NOT_FOUND;
}
ce = (struct cmos_entries*)((unsigned char *)ct + ct->header_length);
@@ -225,13 +240,19 @@ enum cb_err get_option(void *dest, const char *name)
}
if (!found) {
printk(BIOS_DEBUG, "WARNING: No CMOS option '%s'.\n", name);
+ UNLOCK_NVRAM_CBFS_SPINLOCK
return CB_CMOS_OPTION_NOT_FOUND;
}
- if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS)
+ if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS) {
+ UNLOCK_NVRAM_CBFS_SPINLOCK
return CB_CMOS_ACCESS_ERROR;
- if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC))
+ }
+ if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC)) {
+ UNLOCK_NVRAM_CBFS_SPINLOCK
return CB_CMOS_CHECKSUM_INVALID;
+ }
+ UNLOCK_NVRAM_CBFS_SPINLOCK
return CB_SUCCESS;
}