mb/google/dedede: Add dedede mainboard

Add mainboard stubs for Dedede. More functionalities will be added later.

BUG=b:144768001
TEST=Build test.

Change-Id: I7e6cb8adaee7b6bb95e9a96f96466646a78bd0fc
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38277
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

11 files changed, 187 insertions, 0 deletions

diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig
new file mode 100644
index 0000000000..02e4e51a77
--- /dev/null
+++ b/src/mainboard/google/dedede/Kconfig
@@ -0,0 +1,35 @@
+config BOARD_GOOGLE_BASEBOARD_DEDEDE
+	def_bool n
+	select SOC_INTEL_JASPERLAKE
+
+if BOARD_GOOGLE_BASEBOARD_DEDEDE
+
+config BASEBOARD_DEDEDE_LAPTOP
+	def_bool n
+	select SYSTEM_TYPE_LAPTOP
+
+config DEVICETREE
+	string
+	default "variants/baseboard/devicetree.cb"
+
+config MAINBOARD_DIR
+	string
+	default "google/dedede"
+
+config MAINBOARD_FAMILY
+	string
+	default "Google_Dedede" if BOARD_GOOGLE_DEDEDE
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "dedede" if BOARD_GOOGLE_DEDEDE
+
+config MAX_CPUS
+	int
+	default 4
+
+config UART_FOR_CONSOLE
+	int
+	default 2
+
+endif #BOARD_GOOGLE_BASEBOARD_DEDEDE
diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name
new file mode 100644
index 0000000000..4bf440d3cd
--- /dev/null
+++ b/src/mainboard/google/dedede/Kconfig.name
@@ -0,0 +1,5 @@
+config BOARD_GOOGLE_DEDEDE
+	bool "Dedede"
+	select BOARD_GOOGLE_BASEBOARD_DEDEDE
+	select BASEBOARD_DEDEDE_LAPTOP
+	select BOARD_ROMSIZE_KB_32768
diff --git a/src/mainboard/google/dedede/Makefile.inc b/src/mainboard/google/dedede/Makefile.inc
new file mode 100644
index 0000000000..c2fc4198ef
--- /dev/null
+++ b/src/mainboard/google/dedede/Makefile.inc
@@ -0,0 +1,6 @@
+bootblock-y += bootblock.c
+
+ramstage-y += mainboard.c
+
+subdirs-y += variants/baseboard
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
diff --git a/src/mainboard/google/dedede/board_info.txt b/src/mainboard/google/dedede/board_info.txt
new file mode 100644
index 0000000000..db769af716
--- /dev/null
+++ b/src/mainboard/google/dedede/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Google
+Board name: Dedede
+Category: laptop
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/google/dedede/bootblock.c b/src/mainboard/google/dedede/bootblock.c
new file mode 100644
index 0000000000..11186f775c
--- /dev/null
+++ b/src/mainboard/google/dedede/bootblock.c
@@ -0,0 +1,14 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2020 The coreboot project Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <bootblock_common.h>
+
+void bootblock_mainboard_init(void)
+{
+	/* TODO: Perform mainboard initialization */
+}
diff --git a/src/mainboard/google/dedede/chromeos.fmd b/src/mainboard/google/dedede/chromeos.fmd
new file mode 100644
index 0000000000..60ea3ded64
--- /dev/null
+++ b/src/mainboard/google/dedede/chromeos.fmd
@@ -0,0 +1,47 @@
+FLASH@0xfe000000 0x2000000 {
+	SI_ALL@0x0 0x500000 {
+		SI_DESC@0x0 0x1000
+		SI_ME@0x1000 0x4ff000
+	}
+	SI_BIOS@0x500000 0x1b00000 {
+		# Place RW_LEGACY at the start of BIOS region such that the rest
+		# of BIOS regions start at 16MiB boundary. Since this is a 32MiB
+		# SPI flash only the top 16MiB actually gets memory mapped.
+		RW_LEGACY(CBFS)@0x0 0xf00000
+		RW_SECTION_A@0xf00000 0x3e0000 {
+			VBLOCK_A@0x0 0x10000
+			FW_MAIN_A(CBFS)@0x10000 0x3cffc0
+			RW_FWID_A@0x3dffc0 0x40
+		}
+		RW_SECTION_B@0x12e0000 0x3e0000 {
+			VBLOCK_B@0x0 0x10000
+			FW_MAIN_B(CBFS)@0x10000 0x3cffc0
+			RW_FWID_B@0x3dffc0 0x40
+		}
+		RW_MISC@0x16c0000 0x40000 {
+			UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 {
+				RECOVERY_MRC_CACHE@0x0 0x10000
+				RW_MRC_CACHE@0x10000 0x20000
+			}
+			RW_ELOG(PRESERVE)@0x30000 0x4000
+			RW_SHARED@0x34000 0x4000 {
+				SHARED_DATA@0x0 0x2000
+				VBLOCK_DEV@0x2000 0x2000
+			}
+			RW_VPD(PRESERVE)@0x38000 0x2000
+			RW_NVRAM(PRESERVE)@0x3a000 0x6000
+		}
+		# Make WP_RO region align with SPI vendor
+		# memory protected range specification.
+		WP_RO@0x1700000 0x400000 {
+			RO_VPD(PRESERVE)@0x0 0x4000
+			RO_SECTION@0x4000 0x3fc000 {
+				FMAP@0x0 0x800
+				RO_FRID@0x800 0x40
+				RO_FRID_PAD@0x840 0x7c0
+				GBB@0x1000 0x3000
+				COREBOOT(CBFS)@0x4000 0x3f8000
+			}
+		}
+	}
+}
diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c
new file mode 100644
index 0000000000..51b1aa4346
--- /dev/null
+++ b/src/mainboard/google/dedede/mainboard.c
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2020 The coreboot project Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <device/device.h>
+
+static void mainboard_init(void *chip_info)
+{
+	/* TODO: Perform mainboard initialization */
+}
+
+static void mainboard_enable(struct device *dev)
+{
+	/* TODO: Enable mainboard */
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/google/dedede/romstage.c b/src/mainboard/google/dedede/romstage.c
new file mode 100644
index 0000000000..bba6e1a320
--- /dev/null
+++ b/src/mainboard/google/dedede/romstage.c
@@ -0,0 +1,15 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2020 The coreboot project Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <fsp/api.h>
+#include <soc/romstage.h>
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+	/* ToDo : Fill FSP-M memory params */
+}
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
new file mode 100644
index 0000000000..eb9dc1cffb
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb
@@ -0,0 +1,5 @@
+chip soc/intel/tigerlake
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+end
diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h
new file mode 100644
index 0000000000..55faf01850
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/gpio.h
@@ -0,0 +1,15 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2020 The coreboot project Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef __BASEBOARD_GPIO_H__
+#define __BASEBOARD_GPIO_H__
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+#endif /* __BASEBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h
new file mode 100644
index 0000000000..b326ec0468
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h
@@ -0,0 +1,15 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2020 The coreboot project Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef __BASEBOARD_VARIANTS_H__
+#define __BASEBOARD_VARIANTS_H__
+
+#include <soc/gpio.h>
+#include <stdint.h>
+
+#endif /*__BASEBOARD_VARIANTS_H__ */