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authorArthur Heymans <arthur@aheymans.xyz>2018-11-29 02:47:06 +0100
committerPatrick Georgi <pgeorgi@google.com>2018-12-22 11:47:25 +0000
commit8616442150f6a4777ccad9c5b29b8bbfa4be5067 (patch)
tree660305fc3a437060b9c95bf23f9a05b35ef32366
parente4aadd323cb3bc2fefd34d28d9d5bfd7c59ea136 (diff)
downloadcoreboot-8616442150f6a4777ccad9c5b29b8bbfa4be5067.tar.xz
soc/intel/fsp_broadwell_de: Select RELOCATABLE_RAMSTAGE
Tested on wedge100s. Change-Id: I0dcbce230c151cecbbbeec581964cd5f44fbe046 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29911 Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/intel/fsp_broadwell_de/Kconfig1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig
index fe0fa8d12a..197e365f74 100644
--- a/src/soc/intel/fsp_broadwell_de/Kconfig
+++ b/src/soc/intel/fsp_broadwell_de/Kconfig
@@ -15,7 +15,6 @@ config CPU_SPECIFIC_OPTIONS
select SOUTHBRIDGE_INTEL_COMMON
select SOUTHBRIDGE_INTEL_COMMON_SPI
select SOUTHBRIDGE_INTEL_COMMON_RESET
- select NO_RELOCATABLE_RAMSTAGE
select PARALLEL_MP
select SMP
select IOAPIC