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authorAngel Pons <th3fanbus@gmail.com>2020-06-21 15:25:01 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-07-10 12:49:55 +0000
commit8642c659e174e3838058762e5082adc778912c02 (patch)
treeb9c354a517a1df79bfb2956fb95e9210bc2406c4
parente8ea97c945408f9c3185367c9861f458b00fd7ab (diff)
downloadcoreboot-8642c659e174e3838058762e5082adc778912c02.tar.xz
sb/intel/i82801jx/Makefile.inc: Sort entries
Sort them by stage execution order, then alphabetically. Place more complex rules at the end. Tested with BUILD_TIMELESS=1, Intel DG43GT remains identical. Change-Id: I1b36d6c0b2e615938272d65456cf10be54f66c38 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42648 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/southbridge/intel/i82801jx/Makefile.inc16
1 files changed, 8 insertions, 8 deletions
diff --git a/src/southbridge/intel/i82801jx/Makefile.inc b/src/southbridge/intel/i82801jx/Makefile.inc
index 253a5a1b05..8edbf4f8a2 100644
--- a/src/southbridge/intel/i82801jx/Makefile.inc
+++ b/src/southbridge/intel/i82801jx/Makefile.inc
@@ -5,23 +5,23 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801JX),y)
bootblock-y += bootblock.c
bootblock-y += early_init.c
-ramstage-y += i82801jx.c
+romstage-y += early_init.c
+romstage-y += early_smbus.c
+
ramstage-y += fadt.c
-ramstage-y += pci.c
+ramstage-y += hdaudio.c
+ramstage-y += i82801jx.c
ramstage-y += lpc.c
+ramstage-y += pci.c
ramstage-y += pcie.c
-ramstage-y += usb_ehci.c
ramstage-y += sata.c
-ramstage-y += hdaudio.c
-ramstage-y += thermal.c
ramstage-y += smbus.c
+ramstage-y += thermal.c
+ramstage-y += usb_ehci.c
ramstage-y += ../common/pciehp.c
ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
smm-y += smihandler.c
-romstage-y += early_init.c
-romstage-y += early_smbus.c
-
endif