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authorAndre Heider <a.heider@gmail.com>2018-02-16 12:44:42 +0100
committerMartin Roth <martinroth@google.com>2018-02-20 20:35:45 +0000
commit86fd16cc0b755fb874777b7da61076322f903805 (patch)
tree5b48be008bac5ea619d8954e5e24a8fd7ccbb332
parentc9aa0c3d07f168963919cf850171ba0ea7d4fb4f (diff)
downloadcoreboot-86fd16cc0b755fb874777b7da61076322f903805.tar.xz
soc/nvidia/tegra210: add console UART helper functions
These small helper functions aim at supporting the user setting CONFIG_CONSOLE_SERIAL_TEGRA210_UARTx. Change-Id: I71423a0424927ff383bcbf194c9fbaa452d810a1 Signed-off-by: Andre Heider <a.heider@gmail.com> Reviewed-on: https://review.coreboot.org/23795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
-rw-r--r--src/soc/nvidia/tegra210/include/soc/console_uart.h113
1 files changed, 113 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra210/include/soc/console_uart.h b/src/soc/nvidia/tegra210/include/soc/console_uart.h
new file mode 100644
index 0000000000..fc30481326
--- /dev/null
+++ b/src/soc/nvidia/tegra210/include/soc/console_uart.h
@@ -0,0 +1,113 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Andre Heider <a.heider@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_CONSOLE_UART_H__
+#define __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_CONSOLE_UART_H__
+
+#include <soc/clock.h>
+
+enum console_uart_id {
+ UART_ID_NONE = -1,
+ UART_ID_A = 0,
+ UART_ID_B = 1,
+ UART_ID_C = 2,
+ UART_ID_D = 3,
+ UART_ID_E = 4,
+};
+
+static inline enum console_uart_id console_uart_get_id(void)
+{
+ if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_TEGRA210_UARTA))
+ return UART_ID_A;
+
+ if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_TEGRA210_UARTB))
+ return UART_ID_B;
+
+ if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_TEGRA210_UARTC))
+ return UART_ID_C;
+
+ if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_TEGRA210_UARTD))
+ return UART_ID_D;
+
+ if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_TEGRA210_UARTE))
+ return UART_ID_E;
+
+ return UART_ID_NONE;
+}
+
+static inline void *console_uart_clk_rst_reg(void)
+{
+ switch (console_uart_get_id()) {
+ case UART_ID_NONE:
+ return NULL;
+ case UART_ID_A:
+ return CLK_RST_REG(clk_src_uarta);
+ case UART_ID_B:
+ return CLK_RST_REG(clk_src_uartb);
+ case UART_ID_C:
+ return CLK_RST_REG(clk_src_uartc);
+ case UART_ID_D:
+ return CLK_RST_REG(clk_src_uartd);
+ case UART_ID_E:
+ return CLK_RST_REG(clk_src_uarte);
+ }
+
+ return NULL;
+}
+
+static inline uint32_t console_uart_clk_src_dev_id(void)
+{
+ switch (console_uart_get_id()) {
+ case UART_ID_NONE:
+ return 0;
+ case UART_ID_A:
+ return CLK_SRC_DEV_ID(UARTA, PLLP);
+ case UART_ID_B:
+ return CLK_SRC_DEV_ID(UARTB, PLLP);
+ case UART_ID_C:
+ return CLK_SRC_DEV_ID(UARTC, PLLP);
+ case UART_ID_D:
+ return CLK_SRC_DEV_ID(UARTD, PLLP);
+ case UART_ID_E:
+ return CLK_SRC_DEV_ID(UARTE, PLLP);
+ }
+
+ return 0;
+}
+
+static inline void console_uart_clock_enable_clear_reset(void)
+{
+ switch (console_uart_get_id()) {
+ case UART_ID_NONE:
+ return;
+ case UART_ID_A:
+ clock_enable_clear_reset_l(CLK_L_UARTA);
+ break;
+ case UART_ID_B:
+ clock_enable_clear_reset_l(CLK_L_UARTB);
+ break;
+ case UART_ID_C:
+ clock_enable_clear_reset_h(CLK_H_UARTC);
+ break;
+ case UART_ID_D:
+ clock_enable_clear_reset_u(CLK_U_UARTD);
+ break;
+ case UART_ID_E:
+ clock_enable_clear_reset_u(CLK_U_UARTE);
+ break;
+ }
+}
+
+#endif /* __SOC_NVIDIA_TEGRA210_INCLUDE_SOC_CONSOLE_UART_H__ */