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authorKyösti Mälkki <kyosti.malkki@gmail.com>2013-07-07 11:30:48 +0300
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-07-10 23:14:28 +0200
commit8b95c134207de9573f8e5eb758e5cee51741604a (patch)
tree8d49f7f9ce75bf9f0ae9ba26883588753e764f00
parent3ad5a9b97f2d66764880e0cf01b1833d39ddd5ce (diff)
downloadcoreboot-8b95c134207de9573f8e5eb758e5cee51741604a.tar.xz
AMD: Kconfig cleanup
Change-Id: Ie347b32575c26133d52c275622d29d1cd4c6c0c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3623 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
-rwxr-xr-xsrc/cpu/amd/agesa/family12/Kconfig12
-rw-r--r--src/cpu/amd/agesa/family14/Kconfig14
-rw-r--r--src/cpu/amd/agesa/family15/Kconfig5
-rw-r--r--src/cpu/amd/agesa/family15tn/Kconfig19
-rw-r--r--src/cpu/amd/model_10xxx/Kconfig1
-rw-r--r--src/cpu/amd/socket_AM2r2/Kconfig10
-rw-r--r--src/cpu/amd/socket_AM3/Kconfig9
-rw-r--r--src/cpu/amd/socket_ASB2/Kconfig10
-rw-r--r--src/cpu/amd/socket_C32/Kconfig9
-rw-r--r--src/cpu/amd/socket_F_1207/Kconfig10
10 files changed, 32 insertions, 67 deletions
diff --git a/src/cpu/amd/agesa/family12/Kconfig b/src/cpu/amd/agesa/family12/Kconfig
index 1adf5eca31..757db9a20c 100755
--- a/src/cpu/amd/agesa/family12/Kconfig
+++ b/src/cpu/amd/agesa/family12/Kconfig
@@ -22,49 +22,43 @@ config CPU_AMD_AGESA_FAMILY12
select PCI_IO_CFG_EXT
select X86_AMD_FIXED_MTRRS
+if CPU_AMD_AGESA_FAMILY12
+
config CPU_ADDR_BITS
int
default 48
- depends on CPU_AMD_AGESA_FAMILY12
config CPU_SOCKET_TYPE
hex
default 0x10
- depends on CPU_AMD_AGESA_FAMILY12
# DDR2 and REG
config DIMM_SUPPORT
hex
default 0x0104
- depends on CPU_AMD_AGESA_FAMILY12
config EXT_RT_TBL_SUPPORT
bool
default n
- depends on CPU_AMD_AGESA_FAMILY12
config EXT_CONF_SUPPORT
bool
default n
- depends on CPU_AMD_AGESA_FAMILY12
config CBB
hex
default 0x0
- depends on CPU_AMD_AGESA_FAMILY12
config CDB
hex
default 0x18
- depends on CPU_AMD_AGESA_FAMILY12
config XIP_ROM_SIZE
hex
default 0x80000
- depends on CPU_AMD_AGESA_FAMILY12
config HAVE_INIT_TIMER
bool
default y
- depends on CPU_AMD_AGESA_FAMILY12
+endif
diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig
index dea839ea51..7acd520a2b 100644
--- a/src/cpu/amd/agesa/family14/Kconfig
+++ b/src/cpu/amd/agesa/family14/Kconfig
@@ -22,54 +22,48 @@ config CPU_AMD_AGESA_FAMILY14
select PCI_IO_CFG_EXT
select X86_AMD_FIXED_MTRRS
+if CPU_AMD_AGESA_FAMILY14
+
config CPU_ADDR_BITS
int
default 36
- depends on CPU_AMD_AGESA_FAMILY14
config CPU_SOCKET_TYPE
hex
default 0x10
- depends on CPU_AMD_AGESA_FAMILY14
# DDR2 and REG
config DIMM_SUPPORT
hex
default 0x0104
- depends on CPU_AMD_AGESA_FAMILY14
config EXT_RT_TBL_SUPPORT
bool
default n
- depends on CPU_AMD_AGESA_FAMILY14
config EXT_CONF_SUPPORT
bool
default n
- depends on CPU_AMD_AGESA_FAMILY14
config CBB
hex
default 0x0
- depends on CPU_AMD_AGESA_FAMILY14
config CDB
hex
default 0x18
- depends on CPU_AMD_AGESA_FAMILY14
config XIP_ROM_SIZE
hex
default 0x80000
- depends on CPU_AMD_AGESA_FAMILY14
config HAVE_INIT_TIMER
bool
default y
- depends on CPU_AMD_AGESA_FAMILY14
config HIGH_SCRATCH_MEMORY_SIZE
hex
# Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000)
default 0x71000
- depends on CPU_AMD_AGESA_FAMILY14
+
+endif
diff --git a/src/cpu/amd/agesa/family15/Kconfig b/src/cpu/amd/agesa/family15/Kconfig
index e20cce8ab3..02991a04e8 100644
--- a/src/cpu/amd/agesa/family15/Kconfig
+++ b/src/cpu/amd/agesa/family15/Kconfig
@@ -22,12 +22,11 @@ config CPU_AMD_AGESA_FAMILY15
select PCI_IO_CFG_EXT
select X86_AMD_FIXED_MTRRS
+if CPU_AMD_AGESA_FAMILY15
+
config CPU_ADDR_BITS
int
default 48
- depends on CPU_AMD_AGESA_FAMILY15
-
-if CPU_AMD_AGESA_FAMILY15
config CPU_AMD_SOCKET_G34
bool
diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig
index d2f5a8c1b2..9885570d88 100644
--- a/src/cpu/amd/agesa/family15tn/Kconfig
+++ b/src/cpu/amd/agesa/family15tn/Kconfig
@@ -22,59 +22,48 @@ config CPU_AMD_AGESA_FAMILY15_TN
select PCI_IO_CFG_EXT
select X86_AMD_FIXED_MTRRS
+if CPU_AMD_AGESA_FAMILY15_TN
+
config CPU_ADDR_BITS
int
default 48
- depends on CPU_AMD_AGESA_FAMILY15_TN
config CPU_SOCKET_TYPE
hex
default 0x10
- depends on CPU_AMD_AGESA_FAMILY15_TN
# DDR2 and REG
config DIMM_SUPPORT
hex
default 0x0104
- depends on CPU_AMD_AGESA_FAMILY15_TN
config EXT_RT_TBL_SUPPORT
bool
default n
- depends on CPU_AMD_AGESA_FAMILY15_TN
config EXT_CONF_SUPPORT
bool
default n
- depends on CPU_AMD_AGESA_FAMILY15_TN
config CBB
hex
default 0x0
- depends on CPU_AMD_AGESA_FAMILY15_TN
config CDB
hex
default 0x18
- depends on CPU_AMD_AGESA_FAMILY15_TN
-
-config XIP_ROM_BASE
- hex
- default 0xfff80000
- depends on CPU_AMD_AGESA_FAMILY15_TN
config XIP_ROM_SIZE
hex
default 0x100000
- depends on CPU_AMD_AGESA_FAMILY15_TN
config HAVE_INIT_TIMER
bool
default y
- depends on CPU_AMD_AGESA_FAMILY15_TN
config HIGH_SCRATCH_MEMORY_SIZE
hex
# Assume the maximum size of stack as (0xA0000 - 0x30000 + 0x1000)
default 0xA1000
- depends on CPU_AMD_AGESA_FAMILY15_TN
+
+endif
diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig
index 23192f1a06..e4367f97f4 100644
--- a/src/cpu/amd/model_10xxx/Kconfig
+++ b/src/cpu/amd/model_10xxx/Kconfig
@@ -7,6 +7,7 @@ config CPU_AMD_MODEL_10XXX
select UDELAY_LAPIC
if CPU_AMD_MODEL_10XXX
+
config CPU_ADDR_BITS
int
default 48
diff --git a/src/cpu/amd/socket_AM2r2/Kconfig b/src/cpu/amd/socket_AM2r2/Kconfig
index 900bb2bc28..8379063939 100644
--- a/src/cpu/amd/socket_AM2r2/Kconfig
+++ b/src/cpu/amd/socket_AM2r2/Kconfig
@@ -6,32 +6,30 @@ config CPU_AMD_SOCKET_AM2R2
select CACHE_AS_RAM
select X86_AMD_FIXED_MTRRS
+if CPU_AMD_SOCKET_AM2R2
+
config CPU_SOCKET_TYPE
hex
default 0x11
- depends on CPU_AMD_SOCKET_AM2R2
config EXT_RT_TBL_SUPPORT
bool
default n
- depends on CPU_AMD_SOCKET_AM2R2
config EXT_CONF_SUPPORT
bool
default n
- depends on CPU_AMD_SOCKET_AM2R2
config CBB
hex
default 0x0
- depends on CPU_AMD_SOCKET_AM2R2
config CDB
hex
default 0x18
- depends on CPU_AMD_SOCKET_AM2R2
config XIP_ROM_SIZE
hex
default 0x80000
- depends on CPU_AMD_SOCKET_AM2R2
+
+endif
diff --git a/src/cpu/amd/socket_AM3/Kconfig b/src/cpu/amd/socket_AM3/Kconfig
index a0e6593971..4069bfd65d 100644
--- a/src/cpu/amd/socket_AM3/Kconfig
+++ b/src/cpu/amd/socket_AM3/Kconfig
@@ -6,33 +6,30 @@ config CPU_AMD_SOCKET_AM3
select CACHE_AS_RAM
select X86_AMD_FIXED_MTRRS
+if CPU_AMD_SOCKET_AM3
+
config CPU_SOCKET_TYPE
hex
default 0x11
- depends on CPU_AMD_SOCKET_AM3
config EXT_RT_TBL_SUPPORT
bool
default n
- depends on CPU_AMD_SOCKET_AM3
config EXT_CONF_SUPPORT
bool
default n
- depends on CPU_AMD_SOCKET_AM3
config CBB
hex
default 0x0
- depends on CPU_AMD_SOCKET_AM3
config CDB
hex
default 0x18
- depends on CPU_AMD_SOCKET_AM3
config XIP_ROM_SIZE
hex
default 0x80000
- depends on CPU_AMD_SOCKET_AM3
+endif
diff --git a/src/cpu/amd/socket_ASB2/Kconfig b/src/cpu/amd/socket_ASB2/Kconfig
index dbd952caf3..a73a29b58c 100644
--- a/src/cpu/amd/socket_ASB2/Kconfig
+++ b/src/cpu/amd/socket_ASB2/Kconfig
@@ -6,32 +6,30 @@ config CPU_AMD_SOCKET_ASB2
select CACHE_AS_RAM
select X86_AMD_FIXED_MTRRS
+if CPU_AMD_SOCKET_ASB2
+
config CPU_SOCKET_TYPE
hex
default 0x13
- depends on CPU_AMD_SOCKET_ASB2
config EXT_RT_TBL_SUPPORT
bool
default n
- depends on CPU_AMD_SOCKET_ASB2
config EXT_CONF_SUPPORT
bool
default n
- depends on CPU_AMD_SOCKET_ASB2
config CBB
hex
default 0x0
- depends on CPU_AMD_SOCKET_ASB2
config CDB
hex
default 0x18
- depends on CPU_AMD_SOCKET_ASB2
config XIP_ROM_SIZE
hex
default 0x80000
- depends on CPU_AMD_SOCKET_ASB2
+
+endif
diff --git a/src/cpu/amd/socket_C32/Kconfig b/src/cpu/amd/socket_C32/Kconfig
index f8e441f1e7..97b37ee814 100644
--- a/src/cpu/amd/socket_C32/Kconfig
+++ b/src/cpu/amd/socket_C32/Kconfig
@@ -6,33 +6,30 @@ config CPU_AMD_SOCKET_C32_NON_AGESA
select CACHE_AS_RAM
select X86_AMD_FIXED_MTRRS
+if CPU_AMD_SOCKET_C32_NON_AGESA
+
config CPU_SOCKET_TYPE
hex
default 0x14
- depends on CPU_AMD_SOCKET_C32_NON_AGESA
config EXT_RT_TBL_SUPPORT
bool
default n
- depends on CPU_AMD_SOCKET_C32_NON_AGESA
config EXT_CONF_SUPPORT
bool
default n
- depends on CPU_AMD_SOCKET_C32_NON_AGESA
config CBB
hex
default 0x0
- depends on CPU_AMD_SOCKET_C32_NON_AGESA
config CDB
hex
default 0x18
- depends on CPU_AMD_SOCKET_C32_NON_AGESA
config XIP_ROM_SIZE
hex
default 0x80000
- depends on CPU_AMD_SOCKET_C32_NON_AGESA
+endif
diff --git a/src/cpu/amd/socket_F_1207/Kconfig b/src/cpu/amd/socket_F_1207/Kconfig
index c80b5ed0f4..c36c33c61d 100644
--- a/src/cpu/amd/socket_F_1207/Kconfig
+++ b/src/cpu/amd/socket_F_1207/Kconfig
@@ -5,32 +5,30 @@ config CPU_AMD_SOCKET_F_1207
select CACHE_AS_RAM
select X86_AMD_FIXED_MTRRS
+if CPU_AMD_SOCKET_F_1207
+
config CPU_SOCKET_TYPE
hex
default 0x10
- depends on CPU_AMD_SOCKET_F_1207
config EXT_RT_TBL_SUPPORT
bool
default n
- depends on CPU_AMD_SOCKET_F_1207
config EXT_CONF_SUPPORT
bool
default n
- depends on CPU_AMD_SOCKET_F_1207
config CBB
hex
default 0x0
- depends on CPU_AMD_SOCKET_F_1207
config CDB
hex
default 0x18
- depends on CPU_AMD_SOCKET_F_1207
config XIP_ROM_SIZE
hex
default 0x80000
- depends on CPU_AMD_SOCKET_F_1207
+
+endif