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| author | Matt Papageorge <matt.papageorge@amd.corp-partner.google.com> | 2020-06-15 11:37:00 -0500 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-07-30 16:26:44 +0000 |
| commit | 8d481b4e9a6ff598ab48f0014b90106d9bf2cea2 (patch) | |
| tree | 04e7e62c8fc2f42024c223af8d43ee81bebbfdf6 | |
| parent | 27c9762f95da4c16721245daf60f924aa066adae (diff) | |
| download | coreboot-8d481b4e9a6ff598ab48f0014b90106d9bf2cea2.tar.xz | |
amd/common/block/spi: Add EFS SPI configurations to Kconfig
The Embedded Firmware Structure should contain SPI speed, mode
and Micron support for the PSP to program. Add Kconfig options
to specify these values to use for future platform changes.
BUG=b:158755102
TEST=Test menuconfig and platform build for Trembyle and Mandolin.
Signed-off-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Change-Id: I78558fa3fa27c70820f0f3d636544127adab6f8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42567
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/amd/common/block/spi/Kconfig | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/spi/Kconfig b/src/soc/amd/common/block/spi/Kconfig index 785e6da6b3..c8f6d1ecf9 100644 --- a/src/soc/amd/common/block/spi/Kconfig +++ b/src/soc/amd/common/block/spi/Kconfig @@ -9,3 +9,46 @@ config SOC_AMD_COMMON_BLOCK_SPI config SOC_AMD_COMMON_BLOCK_SPI_DEBUG bool default n + +config EFS_SPI_READ_MODE + int + range 0 7 + default 2 + help + SPI read mode to be programmed by the PSP. + The numbers in the options below indicate how many wires + are utilized for command, address and data. For instance 1-1-2 + means 1 command, 1 address and 2 data wires. + 0: Normal Read (up to 33M) + 1: Reserved + 2: Dual IO (1-1-2) + 3: Quad IO (1-1-4) + 4: Dual IO (1-2-2) + 5: Quad IO (1-4-4) + 6: Normal Read (up to 66M) + 7: Fast Read + +config EFS_SPI_SPEED + int + range 0 5 + default 0 + help + SPI Fast Speed to be programmed by the PSP. + 0: 66.66Mhz + 1: 33.33MHz + 2: 22.22MHz + 3: 16.66MHz + 4: 100MHz + 5: 800KHz + +config EFS_SPI_MICRON_FLAG + int + range 0 2 + default 0 + help + For Family 17h Model 00h and later SoC the PSP must be aware if a Micron + part is present in EFS. Automatic detection (option 2) is available + for Family 17h Model 30h-3Fh but is unsupported otherwise. + 0: Board does not use Micron parts + 1: Board always uses Micron parts + 2: Micron parts are optional |