summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorMarshall Dawson <marshalldawson3rd@gmail.com>2017-07-10 18:01:40 -0600
committerMartin Roth <martinroth@google.com>2017-07-12 17:42:07 +0000
commit93be41dcc11be7d8a238db4533c01f53af2ea8b8 (patch)
tree589978f0ea27c69b16ec588765215833699f79a1
parentce1b28f96673f1a0e5a969fd71982b70ef823e93 (diff)
downloadcoreboot-93be41dcc11be7d8a238db4533c01f53af2ea8b8.tar.xz
soc/amd/stoneyridge: Update header guards and includes
Rename the guard to better match the new directory structure. Add include files containing typedefs used in the file. Change-Id: I5fe23ce6994603b0ace99fd6ffc5f3eded2880af Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20525 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
-rw-r--r--src/soc/amd/stoneyridge/include/soc/northbridge.h9
1 files changed, 6 insertions, 3 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h
index 9ecbb13a9a..a87d66b845 100644
--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h
@@ -13,8 +13,11 @@
* GNU General Public License for more details.
*/
-#ifndef NORTHBRIDGE_AMD_AGESA_FAM15H_H
-#define NORTHBRIDGE_AMD_AGESA_FAM15H_H
+#ifndef PI_STONEYRIDGE_NORTHBRIDGE_H
+#define PI_STONEYRIDGE_NORTHBRIDGE_H
+
+#include <arch/io.h>
+#include <device/device.h>
void cpu_bus_scan(device_t dev);
void domain_enable_resources(device_t dev);
@@ -23,4 +26,4 @@ void domain_set_resources(device_t dev);
void fam15_finalize(void *chip_info);
void setup_uma_memory(void);
-#endif /* NORTHBRIDGE_AMD_AGESA_FAM15H_H */
+#endif /* PI_STONEYRIDGE_NORTHBRIDGE_H */