summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorDaniel Kurtz <djkurtz@chromium.org>2018-06-06 15:55:16 -0600
committerMartin Roth <martinroth@google.com>2018-06-08 03:26:51 +0000
commit95cb1e72d7a56882b4ebd7a31319c1a71bc58b9c (patch)
tree4b44546f7ae899b1ffb155938446b17600410278
parent1313244ae7537718bfa4fdf1b1155ac9d0ade27c (diff)
downloadcoreboot-95cb1e72d7a56882b4ebd7a31319c1a71bc58b9c.tar.xz
amd/stoneyridge: Set SCI_MAP for SCI enabled GPIOs
By default we use a 1:1 mapping between GEVENT bits and the corresponding SCI_MAP entry. However, we still must program the SCI_MAP entries with the GEVENT number. BUG=b:109759838 TEST=(1) powerd_dbus_suspend (2) move finger on touchpad for ~1 second => system resumes from S3 Change-Id: Ie7be45264f9bfec56efc47a03071fdb924d16b6a Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/26930 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/amd/stoneyridge/gpio.c10
-rw-r--r--src/soc/amd/stoneyridge/include/soc/gpio.h1
2 files changed, 11 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c
index 1b7f0557df..3bb77b7010 100644
--- a/src/soc/amd/stoneyridge/gpio.c
+++ b/src/soc/amd/stoneyridge/gpio.c
@@ -19,6 +19,7 @@
#include <console/console.h>
#include <gpio.h>
#include <soc/gpio.h>
+#include <soc/southbridge.h>
#include <assert.h>
#include <compiler.h>
@@ -97,6 +98,11 @@ static void program_smi(uint32_t flag, int gevent_num)
SMI_SCI_LVL_LOW);
}
+static void route_sci(uint8_t event)
+{
+ smi_write8(SMI_SCI_MAP(event), event);
+}
+
static void get_sci_config_bits(uint32_t flag, uint32_t *edge, uint32_t *level)
{
uint32_t trigger;
@@ -232,6 +238,9 @@ void sb_program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
mux_ptr = (uint8_t *)(uintptr_t)(gpio + AMD_GPIO_MUX);
write8(mux_ptr, mux & AMD_GPIO_MUX_MASK);
+ /* special case if pin 2 is assigned to wake */
+ if ((gpio == 2) && !(mux & AMD_GPIO_MUX_MASK))
+ route_sci(GPIO_2_EVENT);
gpio_ptr = (uint32_t *)gpio_get_address(gpio);
if (control_flags & GPIO_SPECIAL_FLAG) {
@@ -267,6 +276,7 @@ void sb_program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
edge_level |= bit_edge << gevent_num;
direction |= bit_level << gevent_num;
mask |= (1 << gevent_num);
+ route_sci(gevent_num);
break;
default:
printk(BIOS_WARNING, "Error, flags 0x%08x\n",
diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h
index e43f2c7306..6133bf1684 100644
--- a/src/soc/amd/stoneyridge/include/soc/gpio.h
+++ b/src/soc/amd/stoneyridge/include/soc/gpio.h
@@ -368,6 +368,7 @@ enum {
GEVENT_22,
GEVENT_23,
};
+#define GPIO_2_EVENT GEVENT_8
#define GPIO_OUTPUT_OUT_HIGH (GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE)
#define GPIO_OUTPUT_OUT_LOW GPIO_OUTPUT_ENABLE