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authorVladimir Serbinenko <phcoder@gmail.com>2014-02-19 22:07:12 +0100
committerVladimir Serbinenko <phcoder@gmail.com>2014-03-03 20:55:26 +0100
commit9817a37416468cc8a00990e3f431b8d3634f5fcc (patch)
tree46ef52e3a67094ef02755955a579278cd931f4a7
parent7d1996cc4af563f614455db23fe91a6feccd2560 (diff)
downloadcoreboot-9817a37416468cc8a00990e3f431b8d3634f5fcc.tar.xz
nehalem/raminit: Don't touch clock generator in raminit.
Clock generator is mobo-specific. Don't touch it in raminit. Change-Id: Ie114696b7fb13b8daee8dd1393d43bc609e149b3 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5265 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
-rw-r--r--src/mainboard/lenovo/x201/romstage.c15
-rw-r--r--src/northbridge/intel/nehalem/raminit.c37
-rw-r--r--src/northbridge/intel/nehalem/raminit.h1
3 files changed, 29 insertions, 24 deletions
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c
index 07687b8448..1237a5cb7a 100644
--- a/src/mainboard/lenovo/x201/romstage.c
+++ b/src/mainboard/lenovo/x201/romstage.c
@@ -203,6 +203,17 @@ static inline u16 read_acpi16(u32 addr)
return inw(DEFAULT_PMBASE | addr);
}
+static void set_fsb_frequency(void)
+{
+ u8 block[5];
+ u16 fsbfreq = 62879;
+ smbus_block_read(0x69, 0, 5, block);
+ block[0] = fsbfreq;
+ block[1] = fsbfreq >> 8;
+
+ smbus_block_write(0x69, 0, 5, block);
+}
+
void main(unsigned long bist)
{
u32 reg32;
@@ -287,6 +298,10 @@ void main(unsigned long bist)
timestamp_add_now(TS_BEFORE_INITRAM);
+ chipset_init(s3resume);
+
+ set_fsb_frequency();
+
raminit(s3resume, spd_addrmap);
timestamp_add_now(TS_AFTER_INITRAM);
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index c5fe8ba926..c967e3979f 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -3796,28 +3796,11 @@ static void dmi_setup(void)
}
#endif
-#if REAL
-static void
-set_fsb_frequency (void)
-{
- u8 block[5];
- u16 fsbfreq = 62879;
- smbus_block_read(0x69, 0, 5, block);
- block[0] = fsbfreq;
- block[1] = fsbfreq >> 8;
-
- smbus_block_write(0x69, 0, 5, block);
-}
-#endif
-
-void raminit(const int s3resume, const u8 *spd_addrmap)
+void chipset_init(const int s3resume)
{
- unsigned channel, slot, lane, rank;
- int i;
- struct raminfo info;
u8 x2ca8;
- gav(x2ca8 = read_mchbar8(0x2ca8));
+ x2ca8 = read_mchbar8(0x2ca8);
if ((x2ca8 & 1) || (x2ca8 == 8 && !s3resume)) {
printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
write_mchbar8(0x2ca8, 0);
@@ -3879,12 +3862,18 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
pcie_write_config16(NORTHBRIDGE, D0F0_GGC, 0xb50);
gav(read32(DEFAULT_RCBA | 0x3428));
write32(DEFAULT_RCBA | 0x3428, 0x1d);
+}
-#if !REAL
- pre_raminit_5(s3resume);
-#else
- set_fsb_frequency();
-#endif
+void raminit(const int s3resume, const u8 *spd_addrmap)
+{
+ unsigned channel, slot, lane, rank;
+ int i;
+ struct raminfo info;
+ u8 x2ca8;
+ u16 deven;
+
+ x2ca8 = read_mchbar8(0x2ca8);
+ deven = pcie_read_config16(NORTHBRIDGE, D0F0_DEVEN);
memset(&info, 0x5a, sizeof(info));
diff --git a/src/northbridge/intel/nehalem/raminit.h b/src/northbridge/intel/nehalem/raminit.h
index 91f0dea9c1..0485694133 100644
--- a/src/northbridge/intel/nehalem/raminit.h
+++ b/src/northbridge/intel/nehalem/raminit.h
@@ -22,6 +22,7 @@
#include "nehalem.h"
+void chipset_init(const int s3resume);
/* spd_addrmap is array of 4 elements:
Channel 0 Slot 0
Channel 0 Slot 1