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| author | Edward O'Callaghan <quasisec@google.com> | 2020-06-23 14:11:25 +1000 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-06-30 21:19:36 +0000 |
| commit | a5c2b48e13ad2df799aade19e3e4e601f9477063 (patch) | |
| tree | 4f612a912e48fceb244f4059b6aa84dcb78bb163 | |
| parent | 811284125f0a553963de0e849b18cf60b66be5c4 (diff) | |
| download | coreboot-a5c2b48e13ad2df799aade19e3e4e601f9477063.tar.xz | |
mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in dt
BUG=b:159187889
BRANCH=none
TEST=none
Change-Id: I13626a236f1b7385208c4181150f094cbda490ed
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
| -rw-r--r-- | src/mainboard/google/hatch/variants/puff/overridetree.cb | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index ededac42ed..c78364dc9e 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -84,6 +84,18 @@ chip soc/intel/cannonlake register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0 register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4 + # Bitmap for Wake Enable on USB attach/detach + register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ + USB_PORT_WAKE_ENABLE(3) | \ + USB_PORT_WAKE_ENABLE(4) | \ + USB_PORT_WAKE_ENABLE(5) | \ + USB_PORT_WAKE_ENABLE(6)" + register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ + USB_PORT_WAKE_ENABLE(2) | \ + USB_PORT_WAKE_ENABLE(3) | \ + USB_PORT_WAKE_ENABLE(5) | \ + USB_PORT_WAKE_ENABLE(6)" + # Enable eMMC HS400 register "ScsEmmcHs400Enabled" = "1" |