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authorMichael Niewöhner <foss@mniewoehner.de>2019-11-18 19:51:57 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-11-19 12:56:10 +0000
commita9112169267b209e72d5cf274fddb53f5febd7d2 (patch)
tree014c8b7c436e7d622cf9d31c47fb0207f3abc95d
parent6098da9ea81067b91e67793aac05bc534edd5c3b (diff)
downloadcoreboot-a9112169267b209e72d5cf274fddb53f5febd7d2.tar.xz
docs: intel fsp: add memory retraining bug on SPS systems
FSP2.0 forces MRC retraining on cold boot on Intel SPS systems. Change-Id: I3ce812309b46bdb580557916a775043fda63667f Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
-rw-r--r--Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md2
-rw-r--r--Documentation/soc/intel/fsp/index.md6
2 files changed, 7 insertions, 1 deletions
diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md
index adee88acb2..2cb945ae14 100644
--- a/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md
+++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md
@@ -31,7 +31,7 @@ Look at the [flashing tutorial] and the board-specific section.
These issues apply to all boards. Have a look at the board-specific issues, too.
- TianoCore doesn't work with Aspeed NGI, as it's text mode only (Fix is WIP CB:35726)
-- MRC caching does not work with cold boot
+- MRC caching does not work on cold boot with Intel SPS (see [Intel FSP2.0])
## ToDo
diff --git a/Documentation/soc/intel/fsp/index.md b/Documentation/soc/intel/fsp/index.md
index aac7b35a50..769b98b4fc 100644
--- a/Documentation/soc/intel/fsp/index.md
+++ b/Documentation/soc/intel/fsp/index.md
@@ -34,6 +34,11 @@ those are fixed. If possible a workaround is described here as well.
* Workaround: none
* Issue on public tracker: [Issue 22]
+* MRC forces memory re-training on cold boot on boards with Intel SPS
+ * Releases 3.7.1, 3.7.6
+ * Workaround: Flash Intel ME instead of SPS
+ * Issue on public tracker: [Issue 41]
+
### BraswellFsp
* Internal UART can't be disabled using PcdEnableHsuart*
* Release MR2
@@ -66,4 +71,5 @@ those are fixed. If possible a workaround is described here as well.
[Issue 15]: https://github.com/IntelFsp/FSP/issues/15
[Issue 22]: https://github.com/IntelFsp/FSP/issues/22
[Issue 35]: https://github.com/IntelFsp/FSP/issues/35
+[Issue 41]: https://github.com/IntelFsp/FSP/issues/41