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authorElyes HAOUAS <ehaouas@noos.fr>2019-01-18 15:32:39 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-04-11 11:32:07 +0000
commitb217baa4ee08779c855586117207f6799749d379 (patch)
tree3265e25ee342ac633e105221f120a66b0e9c4a9e
parent7fc25c013b91f26933705549d65e29b0301ff51d (diff)
downloadcoreboot-b217baa4ee08779c855586117207f6799749d379.tar.xz
nb/intel/i945: Fix ich7_setup_root_complex_topology
Element Self Description register (ESD) [23:16] is R/WO, so let write the ESD.CID when we start ich7_setup_root_complex_topology. This value is also used to program the R/WO 'Target Component ID' registers of RPxD and HHD. Once it is done, no need to rewrite on them as they become RO. (For more information, please see ICH7 datasheet page 271.) Tested done on 945G-M4 using printk before and after writing. Before this change, writing on those registers had no effect: ESD: 0x0104: 0x00000802 ULD: 0x0110: 0x00000001 ULBA: 0x0118: 0x00000000 RP1D: 0x0120: 0x01000003 RP2D: 0x0130: 0x02000003 RP3D: 0x0140: 0x03000002 RP4D: 0x0150: 0x04000002 HDD: 0x0160: 0x0f000002 RP5D: 0x0170: 0x05000002 RP6D: 0x0180: 0x06000002 Using this patche, those R/WO get the "right" values. i.e., We can see RCBA32(ULBA) is now equal to (uintptr_t)DEFAULT_DMIBAR. ESD: 0x0104: 0x00020802 ULD: 0x0110: 0x01010001 ULBA: 0x0118: 0xfed18000 RP1D: 0x0120: 0x01020003 RP2D: 0x0130: 0x02020003 RP3D: 0x0140: 0x03020002 RP4D: 0x0150: 0x04020002 HDD: 0x0160: 0x0f020002 RP5D: 0x0170: 0x05020002 RP6D: 0x0180: 0x06020002 Change-Id: I3f2199d6da22ce9995496c2a81363710edde81f3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30993 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/northbridge/intel/i945/early_init.c40
1 files changed, 15 insertions, 25 deletions
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 08dd6752d6..0c92c4bd7d 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -341,13 +341,6 @@ static void ich7_setup_dmi_rcrb(void)
RCBA32(V0CTL) = 0x80000001;
RCBA32(V1CAP) = 0x03128010;
- RCBA32(ESD) = 0x00000810;
- RCBA32(RP1D) = 0x01000003;
- RCBA32(RP2D) = 0x02000002;
- RCBA32(RP3D) = 0x03000002;
- RCBA32(RP4D) = 0x04000002;
- RCBA32(HDD) = 0x0f000003;
- RCBA32(RP5D) = 0x05000002;
pci_write_config16(PCI_DEV(0, 0x1c, 0), 0x42, 0x0141);
pci_write_config16(PCI_DEV(0, 0x1c, 4), 0x42, 0x0141);
@@ -361,20 +354,6 @@ static void ich7_setup_dmi_rcrb(void)
reg32 |= (0x40 << 1) | (4 << 17) | (1 << 24) | (1 << 31);
RCBA32(V1CTL) = reg32;
- RCBA32(ESD) |= (2 << 16);
-
- RCBA32(ULD) |= (1 << 24) | (1 << 16);
-
- RCBA32(ULBA) = (uintptr_t)DEFAULT_DMIBAR;
-
- RCBA32(RP1D) |= (2 << 16);
- RCBA32(RP2D) |= (2 << 16);
- RCBA32(RP3D) |= (2 << 16);
- RCBA32(RP4D) |= (2 << 16);
- RCBA32(HDD) |= (2 << 16);
- RCBA32(RP5D) |= (2 << 16);
- RCBA32(RP6D) |= (2 << 16);
-
RCBA32(LCAP) |= (3 << 10);
}
@@ -871,10 +850,21 @@ static void i945_setup_root_complex_topology(void)
static void ich7_setup_root_complex_topology(void)
{
- RCBA32(0x104) = 0x00000802;
- RCBA32(0x110) = 0x00000001;
- RCBA32(0x114) = 0x00000000;
- RCBA32(0x118) = 0x00000000;
+ /* Write the R/WO registers */
+
+ RCBA32(ESD) |= (2 << 16);
+
+ RCBA32(ULD) |= (1 << 24) | (1 << 16);
+
+ RCBA32(ULBA) = (uintptr_t)DEFAULT_DMIBAR;
+ /* Write ESD.CID to TCID */
+ RCBA32(RP1D) |= (2 << 16);
+ RCBA32(RP2D) |= (2 << 16);
+ RCBA32(RP3D) |= (2 << 16);
+ RCBA32(RP4D) |= (2 << 16);
+ RCBA32(HDD) |= (2 << 16);
+ RCBA32(RP5D) |= (2 << 16);
+ RCBA32(RP6D) |= (2 << 16);
}
static void ich7_setup_pci_express(void)