summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorLee Leahy <leroy.p.leahy@intel.com>2017-03-16 16:44:36 -0700
committerLee Leahy <leroy.p.leahy@intel.com>2017-03-17 02:34:52 +0100
commitb439a929392ba54dee43455f6e164b884cb8c308 (patch)
treeffc44834d8ff6144d360a356dab0688e006945af
parent573564cca8cd01cadf179546b8b124694fd3dcbb (diff)
downloadcoreboot-b439a929392ba54dee43455f6e164b884cb8c308.tar.xz
soc/intel/skylake: Wrap lines at 80 columns
Fix the following warning detected by checkpatch: WARNING: line over 80 characters TEST=Build for glados Change-Id: I79341f46ca06ac052f987975ccaf975470d27806 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/18867 Tested-by: build bot (Jenkins) Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
-rw-r--r--src/soc/intel/skylake/bootblock/cache_as_ram.S4
-rw-r--r--src/soc/intel/skylake/bootblock/pch.c4
-rw-r--r--src/soc/intel/skylake/chip.c15
-rw-r--r--src/soc/intel/skylake/chip.h14
-rw-r--r--src/soc/intel/skylake/cpu.c3
-rw-r--r--src/soc/intel/skylake/me.c12
-rw-r--r--src/soc/intel/skylake/opregion.c3
-rw-r--r--src/soc/intel/skylake/smmrelocate.c6
8 files changed, 39 insertions, 22 deletions
diff --git a/src/soc/intel/skylake/bootblock/cache_as_ram.S b/src/soc/intel/skylake/bootblock/cache_as_ram.S
index 3f8f0f0fb9..eb3d390154 100644
--- a/src/soc/intel/skylake/bootblock/cache_as_ram.S
+++ b/src/soc/intel/skylake/bootblock/cache_as_ram.S
@@ -249,8 +249,8 @@ find_llc_subleaf:
* Ensure region to cache meets MTRR requirements for
* size and alignment.
*/
- movl $(0xFFFFFFFF - CONFIG_ROM_SIZE + 1), %edi /* Code region base */
- movl $CONFIG_ROM_SIZE, %eax /* Code region size */
+ movl $(0xFFFFFFFF - CONFIG_ROM_SIZE + 1), %edi /* Code region base */
+ movl $CONFIG_ROM_SIZE, %eax /* Code region size */
cmpl $0, %edi
jz .halt_forever
cmpl $0, %eax
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index 6279cf2b6d..07beae8f9e 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -192,8 +192,8 @@ static void soc_config_pwrmbase(void)
*
* Program "PM Base Address Memory Range Limit" PCR[DMI] + 27ACh[31:16]
* to the value programmed in PMC PCI Offset 48h bit[31:16], this has an
- * implication of making sure the memory allocated to PWRMBASE to be 64KB
- * in size.
+ * implication of making sure the memory allocated to PWRMBASE to be
+ * 64KB in size.
*/
pcr_write32(PID_DMI, R_PCH_PCR_DMI_PMBASEA,
((PCH_PWRM_BASE_ADDRESS & 0xFFFF0000) |
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 6d9dedb730..61975c648c 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -147,14 +147,17 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
params->EnableSata = config->EnableSata;
params->SataMode = config->SataMode;
params->LockDownConfigGlobalSmi = config->LockDownConfigGlobalSmi;
- params->LockDownConfigBiosInterface = config->LockDownConfigBiosInterface;
+ params->LockDownConfigBiosInterface =
+ config->LockDownConfigBiosInterface;
params->LockDownConfigRtcLock = config->LockDownConfigRtcLock;
params->LockDownConfigBiosLock = config->LockDownConfigBiosLock;
params->LockDownConfigSpiEiss = config->LockDownConfigSpiEiss;
params->PchConfigSubSystemVendorId = config->PchConfigSubSystemVendorId;
params->PchConfigSubSystemId = config->PchConfigSubSystemId;
- params->WakeConfigWolEnableOverride = config->WakeConfigWolEnableOverride;
- params->WakeConfigPcieWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx;
+ params->WakeConfigWolEnableOverride =
+ config->WakeConfigWolEnableOverride;
+ params->WakeConfigPcieWakeFromDeepSx =
+ config->WakeConfigPcieWakeFromDeepSx;
params->PmConfigDeepSxPol = config->PmConfigDeepSxPol;
params->PmConfigSlpS3MinAssert = config->PmConfigSlpS3MinAssert;
params->PmConfigSlpS4MinAssert = config->PmConfigSlpS4MinAssert;
@@ -162,11 +165,13 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
params->PmConfigSlpAMinAssert = config->PmConfigSlpAMinAssert;
params->PmConfigPciClockRun = config->PmConfigPciClockRun;
params->PmConfigSlpStrchSusUp = config->PmConfigSlpStrchSusUp;
- params->PmConfigPwrBtnOverridePeriod = config->PmConfigPwrBtnOverridePeriod;
+ params->PmConfigPwrBtnOverridePeriod =
+ config->PmConfigPwrBtnOverridePeriod;
params->PmConfigPwrCycDur = config->PmConfigPwrCycDur;
params->SerialIrqConfigSirqEnable = config->SerialIrqConfigSirqEnable;
params->SerialIrqConfigSirqMode = config->SerialIrqConfigSirqMode;
- params->SerialIrqConfigStartFramePulse = config->SerialIrqConfigStartFramePulse;
+ params->SerialIrqConfigStartFramePulse =
+ config->SerialIrqConfigStartFramePulse;
params->SkipMpInit = config->FspSkipMpInit;
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 17b34b72e8..4aa7ec9f78 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -265,9 +265,10 @@ struct soc_intel_skylake_config {
u8 LockDownConfigBiosLock;
/*
* Enable InSMM.STS (EISS) in SPI If this bit is set, then WPD must be a
- * '1' and InSMM.STS must be '1' also in order to write to BIOS regions of
- * SPI Flash. If this bit is clear, then the InSMM.STS is a don't care. The
- * BIOS must set the EISS bit while BIOS Guard support is enabled.
+ * '1' and InSMM.STS must be '1' also in order to write to BIOS regions
+ * of SPI Flash. If this bit is clear, then the InSMM.STS is a don't
+ * care. The BIOS must set the EISS bit while BIOS Guard support is
+ * enabled.
*/
u8 LockDownConfigSpiEiss;
/* Subsystem Vendor ID of the PCH devices*/
@@ -325,7 +326,8 @@ struct soc_intel_skylake_config {
*/
u8 PmConfigPciClockRun;
/*
- * SLP_X Stretching After SUS Well Power Up. Values 0: Disabled, 1: Enabled
+ * SLP_X Stretching After SUS Well Power Up. Values 0: Disabled,
+ * 1: Enabled
*/
u8 PmConfigSlpStrchSusUp;
/*
@@ -349,7 +351,9 @@ struct soc_intel_skylake_config {
u8 PmConfigPwrCycDur;
/* Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled.*/
u8 SerialIrqConfigSirqEnable;
- /* Serial IRQ Mode Select. Values: 0: PchQuietMode, 1: PchContinuousMode.*/
+ /* Serial IRQ Mode Select. Values: 0: PchQuietMode,
+ * 1: PchContinuousMode.
+ */
u8 SerialIrqConfigSirqMode;
/*
* Start Frame Pulse Width.
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 4c2aa7fc57..447f84a958 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -520,7 +520,8 @@ int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id)
* same microcode during CPU initialization.
*/
msr = rdmsr(MTRR_CAP_MSR);
- return (msr.lo & PRMRR_SUPPORTED) && (current_patch_id == new_patch_id - 1);
+ return (msr.lo & PRMRR_SUPPORTED)
+ && (current_patch_id == new_patch_id - 1);
}
/*
diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c
index 2f94123374..dd734077ce 100644
--- a/src/soc/intel/skylake/me.c
+++ b/src/soc/intel/skylake/me.c
@@ -279,10 +279,12 @@ void intel_me_status(void)
break;
case ME_HFS2_PHASE_BUP: /* Bringup Phase */
- if (hfs2.fields.current_state < ARRAY_SIZE(me_progress_bup_values)
+ if (hfs2.fields.current_state
+ < ARRAY_SIZE(me_progress_bup_values)
&& me_progress_bup_values[hfs2.fields.current_state])
printk(BIOS_DEBUG, "%s",
- me_progress_bup_values[hfs2.fields.current_state]);
+ me_progress_bup_values[
+ hfs2.fields.current_state]);
else
printk(BIOS_DEBUG, "0x%02x", hfs2.fields.current_state);
break;
@@ -335,7 +337,8 @@ void intel_me_status(void)
printk(BIOS_DEBUG, "Corporate\n");
break;
default:
- printk(BIOS_DEBUG, "Unknown (0x%x)\n", hfs3.fields.fw_sku);
+ printk(BIOS_DEBUG, "Unknown (0x%x)\n",
+ hfs3.fields.fw_sku);
}
}
}
@@ -494,7 +497,8 @@ static int recv_heci_packet(union mei_header *head, u32 *packet,
}
/* here is the message */
for (index = 0; index < length; index++)
- packet[index] = me_read_mmio32(MMIO_ME_CB_RW);
+ packet[index] =
+ me_read_mmio32(MMIO_ME_CB_RW);
rec_msg = 1;
*packet_size = head->fields.length;
diff --git a/src/soc/intel/skylake/opregion.c b/src/soc/intel/skylake/opregion.c
index 31987cb261..4539560efd 100644
--- a/src/soc/intel/skylake/opregion.c
+++ b/src/soc/intel/skylake/opregion.c
@@ -33,7 +33,8 @@ int init_igd_opregion(igd_opregion_t *opregion)
memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
sizeof(IGD_OPREGION_SIGNATURE) - 1);
- memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, sizeof(u32));
+ memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild,
+ sizeof(u32));
memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size <
sizeof(opregion->vbt.gvd1) ? vbt->hdr_vbt_size :
sizeof(opregion->vbt.gvd1));
diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c
index 1cc8e54e55..482107b111 100644
--- a/src/soc/intel/skylake/smmrelocate.c
+++ b/src/soc/intel/skylake/smmrelocate.c
@@ -213,7 +213,8 @@ static void fill_in_relocation_params(device_t dev,
/* SMRR has 32-bits of valid address aligned to 4KiB. */
params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
params->smrr_base.hi = 0;
- params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID;
+ params->smrr_mask.lo = (~(tseg_size - 1) & rmask)
+ | MTRR_PHYS_MASK_VALID;
params->smrr_mask.hi = 0;
/* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */
@@ -226,7 +227,8 @@ static void fill_in_relocation_params(device_t dev,
*/
params->emrr_base.lo = emrr_base | MTRR_TYPE_WRBACK;
params->emrr_base.hi = 0;
- params->emrr_mask.lo = (~(emrr_size - 1) & rmask) | MTRR_PHYS_MASK_VALID;
+ params->emrr_mask.lo = (~(emrr_size - 1) & rmask)
+ | MTRR_PHYS_MASK_VALID;
params->emrr_mask.hi = (1 << (phys_bits - 32)) - 1;
/* UNCORE_EMRR has 39 bits of valid address aligned to 4KiB. */