diff options
| author | Uwe Poeche <uwe.poeche@siemens.com> | 2019-04-02 09:18:53 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-04-04 10:37:44 +0000 |
| commit | b4a403630698e480195e3996978f450a9aa88f6d (patch) | |
| tree | fb842b0f5a650facb7bff2567144d800e2ada420 | |
| parent | 2e2fe3cc91d2831c9962e5e96bd5739eba00ea73 (diff) | |
| download | coreboot-b4a403630698e480195e3996978f450a9aa88f6d.tar.xz | |
siemens/mc_apl4: Provide CLK on APL Pin PMU_SUSCLK
This patch provides a clock on Pin PMU_SUSCLK. This is necessary for correct
function of the SMARC module.
Test=mc_apl4 flashed, booted into Linux, ckecked CLK with scope
Change-Id: Ieb1d66b5a09363c9bed2b19e7a204f206ee04158
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32168
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c index 40b2c93230..2bd56b89da 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/gpio.c @@ -131,7 +131,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPI(PMU_SLP_S0_B, UP_20K, DEEP), PAD_CFG_GPI(PMU_SLP_S3_B, UP_20K, DEEP), PAD_CFG_GPI(PMU_SLP_S4_B, UP_20K, DEEP), - PAD_CFG_GPI(PMU_SUSCLK, DN_20K, DEEP), PAD_CFG_GPI(PMU_WAKE_B, DN_20K, DEEP), PAD_CFG_GPI(SUS_STAT_B, DN_20K, DEEP), PAD_CFG_GPI(SUSPWRDNACK, DN_20K, DEEP), @@ -380,6 +379,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPIO_43, UP_20K, DEEP, NF1), /* LPSS_UART1_TXD */ PAD_CFG_NF(GPIO_46, UP_20K, DEEP, NF1), /* LPSS_UART2_RXD */ PAD_CFG_NF(GPIO_47, UP_20K, DEEP, NF1), /* LPSS_UART2_TXD */ + + PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1),/* 32,78 kHz used on SMARC */ }; const struct pad_config *variant_early_gpio_table(size_t *num) |