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authorLi-Ta Lo <ollie@lanl.gov>2004-05-13 20:40:12 +0000
committerLi-Ta Lo <ollie@lanl.gov>2004-05-13 20:40:12 +0000
commitb7ae8cf8a347460df70e7e7bef10611bba5be438 (patch)
tree5a0a6ba2d2b110aaa6476337bdba32930f48c29c
parent6a8745ae578531617deab7c5de04d4566e3d0b45 (diff)
downloadcoreboot-b7ae8cf8a347460df70e7e7bef10611bba5be438.tar.xz
don't enable VGA/ISA here, it is done in device.c:allocate_vga_resource
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1561 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
-rw-r--r--src/southbridge/amd/amd8151/amd8151_agp3.c58
1 files changed, 23 insertions, 35 deletions
diff --git a/src/southbridge/amd/amd8151/amd8151_agp3.c b/src/southbridge/amd/amd8151/amd8151_agp3.c
index b58f7926d4..dfb8a5592b 100644
--- a/src/southbridge/amd/amd8151/amd8151_agp3.c
+++ b/src/southbridge/amd/amd8151/amd8151_agp3.c
@@ -13,56 +13,45 @@ static void agp3bridge_init(device_t dev)
{
uint8_t byte;
- /* Enable BM and IO */
+ /* Enable BM, MEM and IO */
byte = pci_read_config32(dev, 0x04);
- byte |= 0x07;
- pci_write_config8(dev, 0x04, byte);
-
- /* Eable VGA/ISA decoding */
- byte = pci_read_config32(dev, 0x3e);
- byte |= 3<<2;
- pci_write_config8(dev, 0x3e, byte);
+ byte |= 0x07;
+ pci_write_config8(dev, 0x04, byte);
return;
}
static struct device_operations agp3bridge_ops = {
- .read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
.enable_resources = pci_bus_enable_resources,
- .init = agp3bridge_init,
- .scan_bus = pci_scan_bridge,
+ .init = agp3bridge_init,
+ .scan_bus = pci_scan_bridge,
};
static struct pci_driver agp3bridge_driver __pci_driver = {
- .ops = &agp3bridge_ops,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = 0x7455, // AGP Bridge
+ .ops = &agp3bridge_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = 0x7455, // AGP Bridge
};
static void agp3dev_enable(device_t dev)
{
uint32_t value;
- // AGP enable
- value = pci_read_config32(dev, 0xa8);
- value |= (3<<8)|2; //AGP 8x
- pci_write_config32(dev, 0xa8, value);
-/*
- // linkA 8bit-->16bit
- value = pci_read_config32(dev, 0xc4);
- value |= (0x11<<24);
- pci_write_config32(dev, 0xc4, value);
-
- // linkA 200-->600
- value = pci_read_config32(dev, 0xcc);
- value |= (4<<8);
- pci_write_config32(dev, 0xcc, value);
-*/
+ /* AGP enable */
+ value = pci_read_config32(dev, 0xa8);
+ value |= (3<<8)|2; //AGP 8x
+ pci_write_config32(dev, 0xa8, value);
- value = pci_read_config32(dev, 0x4);
- value |= 6;
- pci_write_config32(dev, 0x4, value);
+ /* enable BM and MEM */
+ value = pci_read_config32(dev, 0x4);
+ value |= 6;
+ pci_write_config32(dev, 0x4, value);
+#if 0
+ /* FIXME: should we add agp aperture base and size here ?
+ * or it is done by AGP drivers */
+#endif
}
static struct device_operations agp3dev_ops = {
@@ -77,6 +66,5 @@ static struct device_operations agp3dev_ops = {
static struct pci_driver agp3dev_driver __pci_driver = {
.ops = &agp3dev_ops,
.vendor = PCI_VENDOR_ID_AMD,
- .device = 0x7454, //AGP Device
-
+ .device = 0x7454, //AGP Device
};