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authorStefan Tauner <stefan.tauner@gmx.at>2012-10-13 13:15:04 +0200
committerPatrick Georgi <patrick@georgi-clan.de>2012-10-30 17:55:57 +0100
commitbef3d347e8a21049d72407246a5d4ec1339b5601 (patch)
treecb2205e3d87de70300fc336e146082d8e5200f42
parent335450d0a1f7befe4ca649d7e23dcf8ed15bf314 (diff)
downloadcoreboot-bef3d347e8a21049d72407246a5d4ec1339b5601.tar.xz
Add support for socket LGA775
Change-Id: Ia7ef3a4cbc3638a9c9a48b297e392e4e655b6e6b Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/1581 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
-rw-r--r--src/cpu/intel/Kconfig1
-rw-r--r--src/cpu/intel/Makefile.inc1
-rw-r--r--src/cpu/intel/socket_LGA775/Kconfig28
-rw-r--r--src/cpu/intel/socket_LGA775/Makefile.inc17
-rw-r--r--src/cpu/intel/socket_LGA775/socket_LGA775.c5
5 files changed, 52 insertions, 0 deletions
diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig
index c6dab12ccc..c3cf4c9fa3 100644
--- a/src/cpu/intel/Kconfig
+++ b/src/cpu/intel/Kconfig
@@ -30,4 +30,5 @@ source src/cpu/intel/socket_mPGA604/Kconfig
source src/cpu/intel/socket_PGA370/Kconfig
source src/cpu/intel/socket_441/Kconfig
source src/cpu/intel/socket_LGA771/Kconfig
+source src/cpu/intel/socket_LGA775/Kconfig
source src/cpu/intel/socket_rPGA989/Kconfig
diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc
index 9e498f194a..782c15ab3e 100644
--- a/src/cpu/intel/Makefile.inc
+++ b/src/cpu/intel/Makefile.inc
@@ -20,6 +20,7 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += model_206ax
subdirs-$(CONFIG_CPU_INTEL_SLOT_2) += slot_2
subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1
subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA771) += socket_LGA771
+subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775
#socket_mPGA604_533Mhz
#socket_mPGA604_800Mhz
diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig
new file mode 100644
index 0000000000..dfb3181096
--- /dev/null
+++ b/src/cpu/intel/socket_LGA775/Kconfig
@@ -0,0 +1,28 @@
+config CPU_INTEL_SOCKET_LGA775
+ bool
+
+if CPU_INTEL_SOCKET_LGA775
+
+config SOCKET_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select CPU_INTEL_MODEL_6EX
+ select CPU_INTEL_MODEL_6FX
+ select CPU_INTEL_MODEL_F3X
+ select CPU_INTEL_MODEL_F4X
+# select CPU_INTEL_MODEL_F6X
+# select CPU_INTEL_MODEL_1066X
+ select CPU_INTEL_MODEL_1067X
+ select MMX
+ select SSE
+ select UDELAY_TSC
+ select SIPI_VECTOR_IN_ROM
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x4000 # 16 kB
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xfeffc000 # 4GB - 16MB - DCACHE_RAM_SIZE
+
+endif # CPU_INTEL_SOCKET_LGA775
diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc
new file mode 100644
index 0000000000..100b4d8e93
--- /dev/null
+++ b/src/cpu/intel/socket_LGA775/Makefile.inc
@@ -0,0 +1,17 @@
+ramstage-y += socket_LGA775.c
+subdirs-y += ../model_6ex
+subdirs-y += ../model_6fx
+subdirs-y += ../model_f3x
+subdirs-y += ../model_f4x
+#subdirs-y += ../model_f6x
+#subdirs-y += ../model_1066x
+subdirs-y += ../model_1067x
+subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/smm
+subdirs-y += ../microcode
+subdirs-y += ../hyperthreading
+
+cpu_incs-$(CONFIG_CACHE_AS_RAM) += $(src)/cpu/intel/car/cache_as_ram_ht.inc
diff --git a/src/cpu/intel/socket_LGA775/socket_LGA775.c b/src/cpu/intel/socket_LGA775/socket_LGA775.c
new file mode 100644
index 0000000000..7ec4e5e4b6
--- /dev/null
+++ b/src/cpu/intel/socket_LGA775/socket_LGA775.c
@@ -0,0 +1,5 @@
+#include <device/device.h>
+
+struct chip_operations cpu_intel_socket_LGA775_ops = {
+ CHIP_NAME("Socket LGA775 CPU")
+};