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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-03-09 17:46:39 +1100
committerIdwer Vollering <vidwer@gmail.com>2014-03-09 13:38:49 +0100
commitbfa29dc021f34f96bfe1f995e90834b0042a9784 (patch)
tree9059b23b417110bae239f98df36f4f2c8b763a14
parent8340666cb18322cbf39110b82d83bf02bfa8c856 (diff)
downloadcoreboot-bfa29dc021f34f96bfe1f995e90834b0042a9784.tar.xz
mainboard/jetway/nf81-t56n-lf: Fix GPP missing CLK on PCI bridge.
The platform dependent mainboard.c was incorrectly disabling the second clock signal feeding the GPP ports. This results in spurious hangs by calling the set_pcie_dereset() SB CIMx callback many times. This also stops coreboot from finding the second NIC behind the pci 15.0 bridge. Change-Id: I9f2370f6e05d1c5532fbca8203e32ab1ff15266a Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5355 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
-rw-r--r--src/mainboard/jetway/nf81-t56n-lf/mainboard.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
index b17bc6a0be..44f9c48ee3 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
@@ -65,11 +65,11 @@ static void mainboard_enable(device_t dev)
acpi_slp_type = acpi_get_sleep_type();
#endif
- /* enable GPP CLK0 thru CLK1 */
- /* disable GPP CLK2 thru SLT_GFX_CLK */
+ /* enable GPP CLK0 thru CLK3 (interleaved) */
+ /* disable GPP CLK4 thru SLT_GFX_CLK */
u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
*(misc_mem_clk_cntrl + 0) = 0xFF;
- *(misc_mem_clk_cntrl + 1) = 0x00;
+ *(misc_mem_clk_cntrl + 1) = 0xFF;
*(misc_mem_clk_cntrl + 2) = 0x00;
*(misc_mem_clk_cntrl + 3) = 0x00;
*(misc_mem_clk_cntrl + 4) = 0x00;