t132: Implement clock initialization api for functional units

This api provides a common interface to initialize various clock sources,
dividers as well as enabling the clock for various functional units.

BUG=chrome-os-partner:31251
BRANCH=None
TEST=Compiles successfully for rush and boots till last known good point.

Change-Id: I2b8df5abf7301bc940315427af4cb38a635f07f8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9814f93a9f99fc9df6267167f991ebef427e9ae3
Original-Change-Id: I7abb193d6a9cfa448df1c48c346b4edbad802329
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/211765
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/8921
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

5 files changed, 240 insertions, 3 deletions

diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc
index 617376d598..6bff52ff8e 100644
--- a/src/soc/nvidia/tegra132/Makefile.inc
+++ b/src/soc/nvidia/tegra132/Makefile.inc
@@ -8,6 +8,7 @@ bootblock-y += i2c.c
 bootblock-y += dma.c
 bootblock-y += monotonic_timer.c
 bootblock-y += padconfig.c
+bootblock-y += funitcfg.c
 bootblock-y += reset.c
 bootblock-y += ../tegra/gpio.c
 bootblock-y += ../tegra/i2c.c
@@ -31,6 +32,7 @@ romstage-y += i2c.c
 romstage-y += dma.c
 romstage-y += monotonic_timer.c
 romstage-y += padconfig.c
+romstage-y += funitcfg.c
 romstage-y += romstage.c
 romstage-y += power.c
 romstage-y += sdram.c
@@ -51,6 +53,7 @@ ramstage-y += i2c.c
 ramstage-y += dma.c
 ramstage-y += monotonic_timer.c
 ramstage-y += padconfig.c
+ramstage-y += funitcfg.c
 ramstage-y += reset.c
 ramstage-y += ../tegra/apbmisc.c
 ramstage-y += ../tegra/gpio.c
diff --git a/src/soc/nvidia/tegra132/clock.c b/src/soc/nvidia/tegra132/clock.c
index fb8e85feee..ed5afbaa45 100644
--- a/src/soc/nvidia/tegra132/clock.c
+++ b/src/soc/nvidia/tegra132/clock.c
@@ -576,6 +576,14 @@ void clock_init(void)
 	graphics_pll();
 }
 
+void clock_grp_enable_clear_reset(u32 val, u32* clk_enb_set_reg,
+				  u32 *rst_dev_clr_reg)
+{
+	writel(val, clk_enb_set_reg);
+	udelay(IO_STABILIZATION_DELAY);
+	writel(val, rst_dev_clr_reg);
+}
+
 void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x)
 {
 	if (l)
diff --git a/src/soc/nvidia/tegra132/funitcfg.c b/src/soc/nvidia/tegra132/funitcfg.c
new file mode 100644
index 0000000000..66fe634b6d
--- /dev/null
+++ b/src/soc/nvidia/tegra132/funitcfg.c
@@ -0,0 +1,157 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <soc/addressmap.h>
+#include <soc/funitcfg.h>
+#include <soc/clock.h>
+#include <soc/padconfig.h>
+#include <string.h>
+
+struct clk_set_data {
+	size_t clk_enb_set_offset;
+	size_t rst_dev_clr_offset;
+};
+
+struct funit_cfg_data {
+	const char *name;
+	size_t clk_src_offset;
+	uint8_t clk_data_index;
+	uint32_t clk_enb_val;
+};
+
+enum {
+	CLK_L_SET = 0,
+	CLK_H_SET = 1,
+	CLK_U_SET = 2,
+	CLK_V_SET = 3,
+	CLK_W_SET = 4,
+	CLK_X_SET = 5,
+};
+
+#define CLK_SET_OFFSETS(x)						\
+	{								\
+	offsetof(struct clk_rst_ctlr, clk_enb_##x##_set),		\
+	offsetof(struct clk_rst_ctlr, rst_dev_##x##_clr)		\
+	}
+
+static const struct clk_set_data clk_data_arr[] = {
+	[CLK_L_SET] = CLK_SET_OFFSETS(l),
+	[CLK_H_SET] = CLK_SET_OFFSETS(h),
+	[CLK_U_SET] = CLK_SET_OFFSETS(u),
+	[CLK_V_SET] = CLK_SET_OFFSETS(v),
+	[CLK_W_SET] = CLK_SET_OFFSETS(w),
+	[CLK_X_SET] = CLK_SET_OFFSETS(x),
+};
+
+static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
+
+static const struct funit_cfg_data funit_data[] =  {
+	[FUNIT_SBC1] = {"sbc1", offsetof(struct clk_rst_ctlr, clk_src_sbc1),
+			CLK_H_SET,
+			CLK_H_SBC1},
+	[FUNIT_SBC4] = {"sbc4", offsetof(struct clk_rst_ctlr, clk_src_sbc4),
+			CLK_U_SET,
+			CLK_U_SBC4},
+	[FUNIT_I2C3] = {"i2c3", offsetof(struct clk_rst_ctlr, clk_src_i2c3),
+			CLK_U_SET,
+			CLK_U_I2C3},
+	[FUNIT_I2C5] = {"i2c5", offsetof(struct clk_rst_ctlr, clk_src_i2c5),
+			CLK_H_SET,
+			CLK_H_I2C5},
+	[FUNIT_SDMMC3] = {"sdmmc3", offsetof(struct clk_rst_ctlr, clk_src_sdmmc3),
+			  CLK_U_SET,
+			  CLK_U_SDMMC3},
+	[FUNIT_SDMMC4] = {"sdmmc4", offsetof(struct clk_rst_ctlr, clk_src_sdmmc4),
+			  CLK_L_SET,
+			  CLK_L_SDMMC4},
+};
+
+static inline uint32_t get_clk_src_freq(uint32_t clk_src)
+{
+	uint32_t freq = 0;
+
+	switch(clk_src) {
+	case CLK_M:
+		freq = TEGRA_CLK_M_KHZ;
+		break;
+	case PLLP:
+		freq = TEGRA_PLLP_KHZ;
+		break;
+	default:
+		printk(BIOS_SPEW, "%s ERROR: Unknown clk_src %d\n",
+		       __func__,clk_src);
+	}
+
+	return freq;
+}
+
+void soc_configure_funits(const struct funit_cfg * const entries, size_t num)
+{
+	size_t i;
+	const char *funit_i2c = "i2c";
+	uint32_t clk_div;
+	uint32_t clk_div_mask;
+
+
+	for (i = 0; i < num; i++) {
+		uint8_t *rst_base = (uint8_t*)clk_rst;
+		const struct funit_cfg * const entry = &entries[i];
+		const struct funit_cfg_data *funit;
+		const struct clk_set_data *clk_data;
+		uint32_t *clk_src_reg, *clk_enb_set_reg, *rst_dev_clr_reg;
+		uint32_t clk_src_freq;
+
+		if (entry->funit_index >= FUNIT_INDEX_MAX) {
+			printk(BIOS_ERR, "Error: Index out of bounds\n");
+			continue;
+		}
+
+		funit = &funit_data[entry->funit_index];
+		clk_data = &clk_data_arr[funit->clk_data_index];
+
+		clk_src_reg = (uint32_t*)(rst_base + funit->clk_src_offset);
+		clk_enb_set_reg = (uint32_t*)(rst_base
+					      + clk_data->clk_enb_set_offset);
+		rst_dev_clr_reg = (uint32_t*)(rst_base
+					      + clk_data->rst_dev_clr_offset);
+
+		clk_src_freq = get_clk_src_freq(entry->clk_src_id);
+
+		if (strncmp(funit->name,funit_i2c,strlen(funit_i2c)) == 0) {
+			/* I2C funit */
+			clk_div = get_i2c_clk_div(clk_src_freq,
+						  entry->clk_dev_freq_khz);
+			clk_div_mask = CLK_DIV_MASK_I2C;
+		} else {
+			/* Non I2C */
+			clk_div = get_clk_div(clk_src_freq,entry->clk_dev_freq_khz);
+			clk_div_mask = CLK_DIV_MASK;
+		}
+
+		_clock_set_div(clk_src_reg,funit->name,clk_div,
+			       clk_div_mask,entry->clk_src_id);
+
+		clock_grp_enable_clear_reset(funit->clk_enb_val,
+					     clk_enb_set_reg,
+					     rst_dev_clr_reg);
+
+		soc_configure_pads(entry->pad_cfg,entry->pad_cfg_size);
+	}
+}
diff --git a/src/soc/nvidia/tegra132/include/soc/clock.h b/src/soc/nvidia/tegra132/include/soc/clock.h
index 5259c18011..6f98e3c618 100644
--- a/src/soc/nvidia/tegra132/include/soc/clock.h
+++ b/src/soc/nvidia/tegra132/include/soc/clock.h
@@ -236,9 +236,14 @@ static inline void _clock_set_div(u32 *reg, const char *name, u32 div,
 			src << CLK_SOURCE_SHIFT | div);
 }
 
+#define get_i2c_clk_div(src,freq) (div_round_up(src, (freq) * (0x19 + 1) * 8) - 1)
+#define get_clk_div(src,freq)     CLK_DIVIDER(src,freq)
+#define CLK_DIV_MASK              0xff
+#define CLK_DIV_MASK_I2C          0xffff
+
 #define clock_configure_irregular_source(device, src, freq, src_id) \
 	_clock_set_div(&clk_rst->clk_src_##device, #device, \
-		CLK_DIVIDER(TEGRA_##src##_KHZ, freq), 0xff, src_id)
+		       get_clk_div(TEGRA_##src##_KHZ, freq), CLK_DIV_MASK, src_id)
 
 /* Warning: Some devices just use different bits for the same sources for no
  * apparent reason. *Always* double-check the TRM before trusting this macro. */
@@ -254,8 +259,8 @@ static inline void _clock_set_div(u32 *reg, const char *name, u32 div,
  */
 #define clock_configure_i2c_scl_freq(device, src, freq) \
 	_clock_set_div(&clk_rst->clk_src_##device, #device, \
-		div_round_up(TEGRA_##src##_KHZ, (freq) * (0x19 + 1) * 8) - 1, \
-		0xffff, src)
+		       get_i2c_clk_div(TEGRA_##src##_KHZ, freq),	\
+		       CLK_DIV_MASK_I2C, src)
 
 enum clock_source {  /* Careful: Not true for all sources, always check TRM! */
 	PLLP = 0,
@@ -288,6 +293,7 @@ void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90,
 void clock_cpu0_config(void);
 void clock_halt_avp(void);
 void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x);
+void clock_grp_enable_clear_reset(u32 val, u32* clk_enb_set_reg, u32* rst_dev_clr_reg);
 void clock_reset_l(u32 l);
 void clock_reset_h(u32 h);
 void clock_reset_u(u32 u);
diff --git a/src/soc/nvidia/tegra132/include/soc/funitcfg.h b/src/soc/nvidia/tegra132/include/soc/funitcfg.h
new file mode 100644
index 0000000000..7612d76af3
--- /dev/null
+++ b/src/soc/nvidia/tegra132/include/soc/funitcfg.h
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __SOC_NVIDIA_TEGRA132_FUNIT_CFG_H
+#define __SOC_NVIDIA_TEGRA132_FUNIT_CFG_H
+
+#include <stdint.h>
+#include <soc/nvidia/tegra132/pinmux.h>
+#include <soc/padconfig.h>
+#include <soc/clock.h>
+
+#define FUNIT_INDEX(_name)  FUNIT_##_name
+
+enum {
+	FUNIT_NONE = 0,
+	FUNIT_INDEX(SBC1),
+	FUNIT_INDEX(SBC4),
+	FUNIT_INDEX(I2C3),
+	FUNIT_INDEX(I2C5),
+	FUNIT_INDEX(SDMMC3),
+	FUNIT_INDEX(SDMMC4),
+	FUNIT_INDEX_MAX,
+};
+
+struct funit_cfg {
+	uint32_t funit_index;
+	uint32_t clk_src_id;
+	uint32_t clk_dev_freq_khz;
+	struct pad_config const* pad_cfg;
+	size_t pad_cfg_size;
+};
+
+#define FUNIT_CFG(_funit,_clk_src,_clk_freq,_cfg,_cfg_size)		\
+	{								\
+		.funit_index = FUNIT_INDEX(_funit),			\
+		.clk_src_id = _clk_src,					\
+		.clk_dev_freq_khz = _clk_freq,				\
+		.pad_cfg = _cfg,					\
+		.pad_cfg_size = _cfg_size,				\
+	}
+
+/*
+ * Configure the funits associated with entry according to the configuration.
+ */
+void soc_configure_funits(const struct funit_cfg * const entries, size_t num);
+
+#endif /* __SOC_NVIDIA_TEGRA132_FUNIT_CFG_H */