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| author | Patrick Georgi <pgeorgi@chromium.org> | 2015-05-07 12:29:13 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-05-11 17:43:43 +0200 |
| commit | c96ff45b7fcc16ff65836f0ed1d2780e9fd3b5ef (patch) | |
| tree | 2178178f796d769a0a77e42a4487404fbe22b5a1 | |
| parent | ccbcfd79eca4d55692011d71911eb7efa7672e8d (diff) | |
| download | coreboot-c96ff45b7fcc16ff65836f0ed1d2780e9fd3b5ef.tar.xz | |
nvidia/tegra132: we write tables in ramstage
So that's more precise than "anything non-pre-ram".
Change-Id: I21db536a5ea704c4b087f57d0b761dd3fdf43e3e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10128
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/soc/nvidia/tegra132/uart.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/nvidia/tegra132/uart.c b/src/soc/nvidia/tegra132/uart.c index 386eaf9005..2055c46307 100644 --- a/src/soc/nvidia/tegra132/uart.c +++ b/src/soc/nvidia/tegra132/uart.c @@ -146,7 +146,7 @@ void uart_tx_flush(int idx) tegra132_uart_tx_flush(uart_ptr); } -#ifndef __PRE_RAM__ +#if ENV_RAMSTAGE void uart_fill_lb(void *data) { struct lb_serial serial; |