summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorTimothy Pearson <tpearson@raptorengineeringinc.com>2015-08-11 17:52:31 -0500
committerMartin Roth <martinroth@google.com>2015-11-24 19:28:51 +0100
commitce3456dacd78df10c3bad360deb3ff9bc521aec5 (patch)
tree5ffcd34c365bd58e8ed9dd1b9ee25f2841efb024
parent50001b80f54c3d1cdd926102c68d33e549541205 (diff)
downloadcoreboot-ce3456dacd78df10c3bad360deb3ff9bc521aec5.tar.xz
nb/amd/amdfam10: Fix gart setup not working on Fam15h processors
Change-Id: Ib78620c30502df6add9cc2ea1dbd4fb6dc89203e Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12047 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
-rw-r--r--src/northbridge/amd/amdfam10/misc_control.c34
1 files changed, 26 insertions, 8 deletions
diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c
index ed932a99db..0b312b1c95 100644
--- a/src/northbridge/amd/amdfam10/misc_control.c
+++ b/src/northbridge/amd/amdfam10/misc_control.c
@@ -73,7 +73,7 @@ static void mcf3_read_resources(device_t dev)
}
}
-static void set_agp_aperture(device_t dev)
+static void set_agp_aperture(device_t dev, uint32_t pci_id)
{
struct resource *resource;
@@ -93,7 +93,7 @@ static void set_agp_aperture(device_t dev)
/* Update the other northbriges */
pdev = 0;
- while((pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1203, pdev))) {
+ while ((pdev = dev_find_device(PCI_VENDOR_ID_AMD, pci_id, pdev))) {
/* Store the GART size but don't enable it */
pci_write_config32(pdev, 0x90, gart_acr);
@@ -109,10 +109,19 @@ static void set_agp_aperture(device_t dev)
}
}
-static void mcf3_set_resources(device_t dev)
+static void mcf3_set_resources_fam10h(device_t dev)
{
/* Set the gart apeture */
- set_agp_aperture(dev);
+ set_agp_aperture(dev, 0x1203);
+
+ /* Set the generic PCI resources */
+ pci_dev_set_resources(dev);
+}
+
+static void mcf3_set_resources_fam15h(device_t dev)
+{
+ /* Set the gart apeture */
+ set_agp_aperture(dev, 0x1603);
/* Set the generic PCI resources */
pci_dev_set_resources(dev);
@@ -151,9 +160,18 @@ static void misc_control_init(struct device *dev)
}
-static struct device_operations mcf3_ops = {
+static struct device_operations mcf3_ops_fam10h = {
+ .read_resources = mcf3_read_resources,
+ .set_resources = mcf3_set_resources_fam10h,
+ .enable_resources = pci_dev_enable_resources,
+ .init = misc_control_init,
+ .scan_bus = 0,
+ .ops_pci = 0,
+};
+
+static struct device_operations mcf3_ops_fam15h = {
.read_resources = mcf3_read_resources,
- .set_resources = mcf3_set_resources,
+ .set_resources = mcf3_set_resources_fam15h,
.enable_resources = pci_dev_enable_resources,
.init = misc_control_init,
.scan_bus = 0,
@@ -161,13 +179,13 @@ static struct device_operations mcf3_ops = {
};
static const struct pci_driver mcf3_driver __pci_driver = {
- .ops = &mcf3_ops,
+ .ops = &mcf3_ops_fam10h,
.vendor = PCI_VENDOR_ID_AMD,
.device = 0x1203,
};
static const struct pci_driver mcf3_driver_fam15 __pci_driver = {
- .ops = &mcf3_ops,
+ .ops = &mcf3_ops_fam15h,
.vendor = PCI_VENDOR_ID_AMD,
.device = 0x1603,
};