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authorTing Shen <phoenixshen@google.com>2019-01-28 18:15:00 +0800
committerPatrick Georgi <pgeorgi@google.com>2019-02-05 13:41:45 +0000
commitdff29e0c65462258776b8fb821516faad3ec1394 (patch)
treea711cd01310f677a54f6497be8f8f071b96be54c
parent4929f4361936bcc994044dea5c79619746384d5e (diff)
downloadcoreboot-dff29e0c65462258776b8fb821516faad3ec1394.tar.xz
bootmem: add new memory type for BL31
After CL:31122, we can finally define a memory type specific for BL31, to make sure BL31 is not loaded on other reserved area. Change-Id: Idbd9a7fe4b12af23de1519892936d8d88a000e2c Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://review.coreboot.org/c/31123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
-rw-r--r--src/arch/arm64/arm_tf.c2
-rw-r--r--src/arch/arm64/include/arch/memlayout.h4
-rw-r--r--src/arch/arm64/tables.c5
-rw-r--r--src/include/bootmem.h2
-rw-r--r--src/include/symbols.h4
-rw-r--r--src/lib/bootmem.c3
-rw-r--r--src/soc/cavium/cn81xx/include/soc/memlayout.ld2
-rw-r--r--src/soc/cavium/cn81xx/soc.c7
-rw-r--r--src/soc/mediatek/mt8173/soc.c6
-rw-r--r--src/soc/mediatek/mt8183/include/soc/memlayout.ld2
-rw-r--r--src/soc/nvidia/tegra210/soc.c13
-rw-r--r--src/soc/rockchip/rk3399/include/soc/memlayout.ld1
12 files changed, 41 insertions, 10 deletions
diff --git a/src/arch/arm64/arm_tf.c b/src/arch/arm64/arm_tf.c
index c0526e08d5..3f1aa2a265 100644
--- a/src/arch/arm64/arm_tf.c
+++ b/src/arch/arm64/arm_tf.c
@@ -50,7 +50,7 @@ void arm_tf_run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr)
if (prog_locate(&bl31))
die("BL31 not found");
- if (!selfload(&bl31))
+ if (!selfload_check(&bl31, BM_MEM_BL31))
die("BL31 load failed");
bl31_entry = prog_entry(&bl31);
diff --git a/src/arch/arm64/include/arch/memlayout.h b/src/arch/arm64/include/arch/memlayout.h
index 7fce9aa2f8..a3fdd66e4f 100644
--- a/src/arch/arm64/include/arch/memlayout.h
+++ b/src/arch/arm64/include/arch/memlayout.h
@@ -37,4 +37,8 @@
REGION(stack, addr, size, 16) \
_ = ASSERT(size >= 2K, "stack should be >= 2K, see toolchain.inc");
+#define BL31(addr, size) \
+ REGION(bl31, addr, size, 4K) \
+ _ = ASSERT(size % 4K == 0, "BL31 size must be divisible by 4K!");
+
#endif /* __ARCH_MEMLAYOUT_H */
diff --git a/src/arch/arm64/tables.c b/src/arch/arm64/tables.c
index f36679e67f..ec949fd83b 100644
--- a/src/arch/arm64/tables.c
+++ b/src/arch/arm64/tables.c
@@ -20,6 +20,8 @@
#include <boot/coreboot_tables.h>
#include <symbols.h>
+DECLARE_OPTIONAL_REGION(bl31);
+
void arch_write_tables(uintptr_t coreboot_table)
{
}
@@ -28,6 +30,9 @@ void bootmem_arch_add_ranges(void)
{
bootmem_add_range((uintptr_t)_ttb, _ttb_size, BM_MEM_RAMSTAGE);
+ if (IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) && _bl31_size > 0)
+ bootmem_add_range((uintptr_t)_bl31, _bl31_size, BM_MEM_BL31);
+
if (!IS_ENABLED(CONFIG_COMMON_CBFS_SPI_WRAPPER))
return;
bootmem_add_range((uintptr_t)_postram_cbfs_cache,
diff --git a/src/include/bootmem.h b/src/include/bootmem.h
index 4652d08f20..c935cb919f 100644
--- a/src/include/bootmem.h
+++ b/src/include/bootmem.h
@@ -37,6 +37,7 @@ enum bootmem_type {
BM_MEM_NVS, /* ACPI NVS Memory */
BM_MEM_UNUSABLE, /* Unusable address space */
BM_MEM_VENDOR_RSVD, /* Vendor Reserved */
+ BM_MEM_BL31, /* Arm64 BL31 exectuable */
BM_MEM_TABLE, /* Ram configuration tables are kept in */
/* Tags below this point are ignored for the OS table. */
BM_MEM_OS_CUTOFF = BM_MEM_TABLE,
@@ -53,6 +54,7 @@ enum bootmem_type {
* Bootmem types match to LB_MEM tags, except for the following:
* BM_MEM_RAMSTAGE : Translates to LB_MEM_RAM.
* BM_MEM_PAYLOAD : Translates to LB_MEM_RAM.
+ * BM_MEM_BL31 : Translates to LB_MEM_RESERVED.
*/
void bootmem_write_memory_table(struct lb_memory *mem);
diff --git a/src/include/symbols.h b/src/include/symbols.h
index fc9ef21ecf..abb9fbecbc 100644
--- a/src/include/symbols.h
+++ b/src/include/symbols.h
@@ -114,6 +114,10 @@ extern u8 _pdpt[];
extern u8 _epdpt[];
#define _pdpt_size (_epdpt - _pdpt)
+extern u8 _bl31[];
+extern u8 _ebl31[];
+#define _bl31_size (_ebl31 - _bl31)
+
/* Put this into a .c file accessing a linker script region to mark that region
* as "optional". If it is defined in memlayout.ld (or anywhere else), the
* values from that definition will be used. If not, start, end and size will
diff --git a/src/lib/bootmem.c b/src/lib/bootmem.c
index c804df5973..7cc8fff2e4 100644
--- a/src/lib/bootmem.c
+++ b/src/lib/bootmem.c
@@ -59,6 +59,8 @@ static uint32_t bootmem_to_lb_tag(const enum bootmem_type tag)
return LB_MEM_UNUSABLE;
case BM_MEM_VENDOR_RSVD:
return LB_MEM_VENDOR_RSVD;
+ case BM_MEM_BL31:
+ return LB_MEM_RESERVED;
case BM_MEM_TABLE:
return LB_MEM_TABLE;
default:
@@ -142,6 +144,7 @@ static const struct range_strings type_strings[] = {
{ BM_MEM_NVS, "NVS" },
{ BM_MEM_UNUSABLE, "UNUSABLE" },
{ BM_MEM_VENDOR_RSVD, "VENDOR RESERVED" },
+ { BM_MEM_BL31, "BL31" },
{ BM_MEM_TABLE, "CONFIGURATION TABLES" },
{ BM_MEM_RAMSTAGE, "RAMSTAGE" },
{ BM_MEM_PAYLOAD, "PAYLOAD" },
diff --git a/src/soc/cavium/cn81xx/include/soc/memlayout.ld b/src/soc/cavium/cn81xx/include/soc/memlayout.ld
index e3bf61f1f4..22226176e7 100644
--- a/src/soc/cavium/cn81xx/include/soc/memlayout.ld
+++ b/src/soc/cavium/cn81xx/include/soc/memlayout.ld
@@ -22,7 +22,7 @@ SECTIONS
{
DRAM_START(0x00000000)
/* Secure region 0 - 1MiB */
- REGION(bl31, 0, 0xe0000, 0x1000)
+ BL31(0, 0xe0000)
REGION(sff8104, 0xe0000, 0x20000, 0x1000)
/* Insecure region 1MiB - TOP OF DRAM */
diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c
index 2046d21b11..4b265d7d7b 100644
--- a/src/soc/cavium/cn81xx/soc.c
+++ b/src/soc/cavium/cn81xx/soc.c
@@ -319,18 +319,11 @@ static int dt_platform_fixup(struct device_tree_fixup *fixup,
return 0;
}
-extern u8 _bl31[];
-extern u8 _ebl31[];
extern u8 _sff8104[];
extern u8 _esff8104[];
void bootmem_platform_add_ranges(void)
{
- /* ATF reserved */
- bootmem_add_range((uintptr_t)_bl31,
- ((uintptr_t)_ebl31 - (uintptr_t)_bl31),
- BM_MEM_RESERVED);
-
bootmem_add_range((uintptr_t)_sff8104,
((uintptr_t)_esff8104 - (uintptr_t)_sff8104),
BM_MEM_RESERVED);
diff --git a/src/soc/mediatek/mt8173/soc.c b/src/soc/mediatek/mt8173/soc.c
index 37ceb34fd4..b5c805a595 100644
--- a/src/soc/mediatek/mt8173/soc.c
+++ b/src/soc/mediatek/mt8173/soc.c
@@ -13,10 +13,16 @@
* GNU General Public License for more details.
*/
+#include <bootmem.h>
#include <device/device.h>
#include <symbols.h>
#include <soc/emi.h>
+void bootmem_platform_add_ranges(void)
+{
+ bootmem_add_range(0x101000, 124 * KiB, BM_MEM_BL31);
+}
+
static void soc_read_resources(struct device *dev)
{
ram_resource(dev, 0, (uintptr_t)_dram / KiB, sdram_size() / KiB);
diff --git a/src/soc/mediatek/mt8183/include/soc/memlayout.ld b/src/soc/mediatek/mt8183/include/soc/memlayout.ld
index 2a6d42de63..a547083ebd 100644
--- a/src/soc/mediatek/mt8183/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8183/include/soc/memlayout.ld
@@ -47,4 +47,6 @@ SECTIONS
DRAM_START(0x40000000)
POSTRAM_CBFS_CACHE(0x40000000, 2M)
RAMSTAGE(0x40200000, 256K)
+
+ BL31(0x54600000, 0x60000)
}
diff --git a/src/soc/nvidia/tegra210/soc.c b/src/soc/nvidia/tegra210/soc.c
index 71532be989..619d27fb11 100644
--- a/src/soc/nvidia/tegra210/soc.c
+++ b/src/soc/nvidia/tegra210/soc.c
@@ -16,6 +16,7 @@
#include <arch/io.h>
#include <arch/cache.h>
+#include <bootmem.h>
#include <bootmode.h>
#include <bootstate.h>
#include <console/console.h>
@@ -33,13 +34,23 @@
#include "chip.h"
+void bootmem_platform_add_ranges(void)
+{
+ uintptr_t begin;
+ size_t size;
+ carveout_range(CARVEOUT_TZ, &begin, &size);
+ if (size == 0)
+ return;
+ bootmem_add_range(begin * MiB, size * MiB, BM_MEM_BL31);
+}
+
static void soc_read_resources(struct device *dev)
{
unsigned long index = 0;
int i; uintptr_t begin, end;
size_t size;
- for (i = 0; i < CARVEOUT_NUM; i++) {
+ for (i = CARVEOUT_TZ + 1; i < CARVEOUT_NUM; i++) {
carveout_range(i, &begin, &size);
if (size == 0)
continue;
diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld
index e181a35307..01e352f230 100644
--- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld
@@ -19,6 +19,7 @@
SECTIONS
{
DRAM_START(0x00000000)
+ BL31(0, 0x100000)
POSTRAM_CBFS_CACHE(0x00100000, 1M)
RAMSTAGE(0x00300000, 256K)
DMA_COHERENT(0x10000000, 2M)