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| author | Aaron Durbin <adurbin@chromium.org> | 2014-11-25 17:23:22 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-10 20:45:40 +0200 |
| commit | e37c18f891920be529b90eda856cf7389f2c8bc3 (patch) | |
| tree | ea42408b162d395703193c2e5803d71e0025eea6 | |
| parent | 1d1a15d87f200bc08a610c5243631b270e8b4e47 (diff) | |
| download | coreboot-e37c18f891920be529b90eda856cf7389f2c8bc3.tar.xz | |
arm64: psci: actually inform SoC layer of CPU_ON entry
psci_soc_init() was added to allow SoC PSCI initialization.
However, actually calling said function was omitted accidentally.
BUG=chrome-os-partner:32136
BRANCH=None
TEST=Built and noted correct on entry point was used.
Change-Id: I84a397e2dabf149fe8f252ef69d0a7362fa1f194
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2a0e6ad41f049bbab483423231db59390894e9b2
Original-Change-Id: I1a4e25fde64ecdc98fa9231f7d9cafc21119630d
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/231935
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9530
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
| -rw-r--r-- | src/arch/arm64/armv8/secmon/psci.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/arm64/armv8/secmon/psci.c b/src/arch/arm64/armv8/secmon/psci.c index 3ba7e73e61..6047abd698 100644 --- a/src/arch/arm64/armv8/secmon/psci.c +++ b/src/arch/arm64/armv8/secmon/psci.c @@ -565,4 +565,7 @@ void psci_init(uintptr_t cpu_on_entry) /* Register PSCI handlers. */ if (smc_register_range(PSCI_CPU_OFF64, PSCI_CPU_ON64, &psci_handler)) printk(BIOS_ERR, "Couldn't register PSCI handler.\n"); + + /* Inform SoC layer of CPU_ON entry point. */ + psci_soc_init(cpu_on_entry); } |