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authorArthur Heymans <arthur@aheymans.xyz>2018-12-22 16:59:44 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-05-15 17:57:33 +0000
commite43972474c0eebc478722f7c371a8c68318f24cf (patch)
tree34abf5f2a18cb350fe4871b4e8509c5da4705d37
parent4d56a0625516ba436903d59d9c0a4a13827d89be (diff)
downloadcoreboot-e43972474c0eebc478722f7c371a8c68318f24cf.tar.xz
soc/intel/broadwell: Enable LPC/SIO setup in bootblock
This allows for serial console during the bootblock and enables bootblock console by default. Change-Id: I7746e4f819486d6142c96bc4c7480076fbfdfbde Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
-rw-r--r--src/mainboard/google/jecht/Makefile.inc4
-rw-r--r--src/mainboard/google/jecht/bootblock.c31
-rw-r--r--src/mainboard/google/jecht/romstage.c12
-rw-r--r--src/soc/intel/broadwell/Kconfig1
-rw-r--r--src/soc/intel/broadwell/bootblock/pch.c49
-rw-r--r--src/soc/intel/broadwell/include/soc/romstage.h1
-rw-r--r--src/soc/intel/broadwell/romstage/pch.c41
-rw-r--r--src/soc/intel/broadwell/romstage/romstage.c9
8 files changed, 83 insertions, 65 deletions
diff --git a/src/mainboard/google/jecht/Makefile.inc b/src/mainboard/google/jecht/Makefile.inc
index 28a284e759..116792fab7 100644
--- a/src/mainboard/google/jecht/Makefile.inc
+++ b/src/mainboard/google/jecht/Makefile.inc
@@ -24,7 +24,9 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c led.c
romstage-y += variants/$(VARIANT_DIR)/pei_data.c
ramstage-y += variants/$(VARIANT_DIR)/pei_data.c
-romstage-y += led.c
+bootblock-y += led.c
+
+bootblock-y += bootblock.c
subdirs-y += variants/$(VARIANT_DIR)
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
diff --git a/src/mainboard/google/jecht/bootblock.c b/src/mainboard/google/jecht/bootblock.c
new file mode 100644
index 0000000000..43725cd747
--- /dev/null
+++ b/src/mainboard/google/jecht/bootblock.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8772f/it8772f.h>
+#include "onboard.h"
+
+void bootblock_mainboard_early_init(void)
+{
+ /* Early SuperIO setup */
+ it8772f_ac_resume_southbridge(IT8772F_SUPERIO_DEV);
+ ite_kill_watchdog(IT8772F_GPIO_DEV);
+ ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE);
+
+ /* Turn On Power LED */
+ set_power_led(LED_ON);
+}
diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c
index 86888c82f8..4fc2ba0c93 100644
--- a/src/mainboard/google/jecht/romstage.c
+++ b/src/mainboard/google/jecht/romstage.c
@@ -39,15 +39,3 @@ void mainboard_post_raminit(struct romstage_params *rp)
if (CONFIG(CHROMEOS))
init_bootmode_straps();
}
-
-void mainboard_pre_console_init(void)
-{
- /* Early SuperIO setup */
- it8772f_ac_resume_southbridge(IT8772F_SUPERIO_DEV);
- ite_kill_watchdog(IT8772F_GPIO_DEV);
- ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE);
-
- /* Turn On Power LED */
- set_power_led(LED_ON);
-
-}
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index b685391af9..d81ab8ac95 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -45,7 +45,6 @@ config CPU_SPECIFIC_OPTIONS
select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
select NO_FIXED_XIP_ROM_SIZE
select C_ENVIRONMENT_BOOTBLOCK
- select NO_BOOTBLOCK_CONSOLE
config PCIEXP_ASPM
bool
diff --git a/src/soc/intel/broadwell/bootblock/pch.c b/src/soc/intel/broadwell/bootblock/pch.c
index 1301610947..590961b361 100644
--- a/src/soc/intel/broadwell/bootblock/pch.c
+++ b/src/soc/intel/broadwell/bootblock/pch.c
@@ -19,6 +19,9 @@
#include <soc/pci_devs.h>
#include <soc/rcba.h>
#include <soc/spi.h>
+#include <reg_script.h>
+#include <soc/pm.h>
+#include <soc/romstage.h>
#include <cpu/intel/car/bootblock.h>
/*
@@ -67,10 +70,56 @@ static void set_spi_speed(void)
SPIBAR8(SPIBAR_SSFC + 2) = ssfc;
}
+const struct reg_script pch_early_init_script[] = {
+ /* Setup southbridge BARs */
+ REG_PCI_WRITE32(RCBA, RCBA_BASE_ADDRESS | 1),
+ REG_PCI_WRITE32(PMBASE, ACPI_BASE_ADDRESS | 1),
+ REG_PCI_WRITE8(ACPI_CNTL, ACPI_EN),
+ REG_PCI_WRITE32(GPIO_BASE, GPIO_BASE_ADDRESS | 1),
+ REG_PCI_WRITE8(GPIO_CNTL, GPIO_EN),
+
+ /* Set COM1/COM2 decode range */
+ REG_PCI_WRITE16(LPC_IO_DEC, 0x0010),
+ /* Enable legacy decode ranges */
+ REG_PCI_WRITE16(LPC_EN, CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN |
+ COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN),
+
+ /* Enable IOAPIC */
+ REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + OIC, 0x0100),
+ /* Read back for posted write */
+ REG_MMIO_READ16(RCBA_BASE_ADDRESS + OIC),
+
+ /* Set HPET address and enable it */
+ REG_MMIO_RMW32(RCBA_BASE_ADDRESS + HPTC, ~3, (1 << 7)),
+ /* Read back for posted write */
+ REG_MMIO_READ32(RCBA_BASE_ADDRESS + HPTC),
+ /* Enable HPET to start counter */
+ REG_MMIO_OR32(HPET_BASE_ADDRESS + 0x10, (1 << 0)),
+
+ /* Disable reset */
+ REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 5)),
+ /* TCO timer halt */
+ REG_IO_OR16(ACPI_BASE_ADDRESS + TCO1_CNT, TCO_TMR_HLT),
+
+ /* Enable upper 128 bytes of CMOS */
+ REG_MMIO_OR32(RCBA_BASE_ADDRESS + RC, (1 << 2)),
+
+ /* Disable unused device (always) */
+ REG_MMIO_OR32(RCBA_BASE_ADDRESS + FD, PCH_DISABLE_ALWAYS),
+
+ REG_SCRIPT_END
+};
+
+static void pch_early_lpc(void)
+{
+ reg_script_run_on_dev(PCH_DEV_LPC, pch_early_init_script);
+}
+
void bootblock_early_southbridge_init(void)
{
map_rcba();
enable_spi_prefetch();
enable_port80_on_lpc();
set_spi_speed();
+ pch_early_lpc();
}
diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h
index d65692ae23..ece3cd8c5a 100644
--- a/src/soc/intel/broadwell/include/soc/romstage.h
+++ b/src/soc/intel/broadwell/include/soc/romstage.h
@@ -50,5 +50,4 @@ int smbus_read_byte(unsigned int device, unsigned int address);
int early_spi_read(u32 offset, u32 size, u8 *buffer);
int early_spi_read_wpsr(u8 *sr);
-void mainboard_pre_console_init(void);
#endif
diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c
index ecdadb7f9b..ef97a1e3fa 100644
--- a/src/soc/intel/broadwell/romstage/pch.c
+++ b/src/soc/intel/broadwell/romstage/pch.c
@@ -27,46 +27,6 @@
#include <soc/smbus.h>
#include <soc/intel/broadwell/chip.h>
-const struct reg_script pch_early_init_script[] = {
- /* Setup southbridge BARs */
- REG_PCI_WRITE32(RCBA, RCBA_BASE_ADDRESS | 1),
- REG_PCI_WRITE32(PMBASE, ACPI_BASE_ADDRESS | 1),
- REG_PCI_WRITE8(ACPI_CNTL, ACPI_EN),
- REG_PCI_WRITE32(GPIO_BASE, GPIO_BASE_ADDRESS | 1),
- REG_PCI_WRITE8(GPIO_CNTL, GPIO_EN),
-
- /* Set COM1/COM2 decode range */
- REG_PCI_WRITE16(LPC_IO_DEC, 0x0010),
- /* Enable legacy decode ranges */
- REG_PCI_WRITE16(LPC_EN, CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN |
- COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN),
-
- /* Enable IOAPIC */
- REG_MMIO_WRITE16(RCBA_BASE_ADDRESS + OIC, 0x0100),
- /* Read back for posted write */
- REG_MMIO_READ16(RCBA_BASE_ADDRESS + OIC),
-
- /* Set HPET address and enable it */
- REG_MMIO_RMW32(RCBA_BASE_ADDRESS + HPTC, ~3, (1 << 7)),
- /* Read back for posted write */
- REG_MMIO_READ32(RCBA_BASE_ADDRESS + HPTC),
- /* Enable HPET to start counter */
- REG_MMIO_OR32(HPET_BASE_ADDRESS + 0x10, (1 << 0)),
-
- /* Disable reset */
- REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 5)),
- /* TCO timer halt */
- REG_IO_OR16(ACPI_BASE_ADDRESS + TCO1_CNT, TCO_TMR_HLT),
-
- /* Enable upper 128 bytes of CMOS */
- REG_MMIO_OR32(RCBA_BASE_ADDRESS + RC, (1 << 2)),
-
- /* Disable unused device (always) */
- REG_MMIO_OR32(RCBA_BASE_ADDRESS + FD, PCH_DISABLE_ALWAYS),
-
- REG_SCRIPT_END
-};
-
const struct reg_script pch_interrupt_init_script[] = {
/*
* GFX INTA -> PIRQA (MSI)
@@ -132,7 +92,6 @@ static void pch_enable_lpc(void)
void pch_early_init(void)
{
- reg_script_run_on_dev(PCH_DEV_LPC, pch_early_init_script);
reg_script_run_on_dev(PCH_DEV_LPC, pch_interrupt_init_script);
pch_enable_lpc();
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 54434a3153..f8571678d8 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -77,13 +77,6 @@ void mainboard_romstage_entry(unsigned long bist)
/* PCH Early Initialization */
pch_early_init();
- /* Call into mainboard pre console init. Needed to enable serial port
- on IT8772 */
- mainboard_pre_console_init();
-
- /* Start console drivers */
- console_init();
-
/* Get power state */
rp.power_state = fill_power_state();
@@ -125,5 +118,3 @@ void mainboard_romstage_entry(unsigned long bist)
mainboard_post_raminit(&rp);
}
-
-void __weak mainboard_pre_console_init(void) {}