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authorMichael Niewöhner <foss@mniewoehner.de>2020-03-13 21:17:21 +0100
committerFelix Held <felix-coreboot@felixheld.de>2020-03-16 22:41:07 +0000
commite6cff0d8304b650f0371938fdb9f545032c8ce16 (patch)
treee2f7c5bd340bebf1308391e5be5dcef0107d3bf2
parent8676c268a033f997e4859fd7608d281f00937c8a (diff)
downloadcoreboot-e6cff0d8304b650f0371938fdb9f545032c8ce16.tar.xz
util/inteltool: ahci: add code for dumping config and SIR registers
This adds the code required to dump config and SIR registers. Change-Id: I3726c52d415ff4dd6b19513b310f11254f7fbf92 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39560 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--util/inteltool/ahci.c54
1 files changed, 54 insertions, 0 deletions
diff --git a/util/inteltool/ahci.c b/util/inteltool/ahci.c
index 09f6427ee4..3a18993e01 100644
--- a/util/inteltool/ahci.c
+++ b/util/inteltool/ahci.c
@@ -60,6 +60,11 @@ static void print_port(const uint8_t *const mmio, size_t port)
int print_ahci(struct pci_dev *ahci)
{
size_t ahci_registers_size = 0, i;
+ size_t ahci_cfg_registers_size = 0;
+ const io_register_t *ahci_cfg_registers;
+ size_t ahci_sir_offset = 0;
+ size_t ahci_sir_registers_size = 0;
+ const io_register_t *ahci_sir_registers;
if (!ahci) {
puts("No SATA device found");
@@ -76,6 +81,55 @@ int print_ahci(struct pci_dev *ahci)
ahci_registers_size = 0x400;
}
+ printf("\n============= AHCI Configuration Registers ==============\n\n");
+ for (i = 0; i < ahci_cfg_registers_size; i++) {
+ switch (ahci_cfg_registers[i].size) {
+ case 4:
+ printf("0x%04x: 0x%08x (%s)\n",
+ ahci_cfg_registers[i].addr,
+ pci_read_long(ahci, ahci_cfg_registers[i].addr),
+ ahci_cfg_registers[i].name);
+ break;
+ case 2:
+ printf("0x%04x: 0x%04x (%s)\n",
+ ahci_cfg_registers[i].addr,
+ pci_read_word(ahci, ahci_cfg_registers[i].addr),
+ ahci_cfg_registers[i].name);
+ break;
+ case 1:
+ printf("0x%04x: 0x%02x (%s)\n",
+ ahci_cfg_registers[i].addr,
+ pci_read_byte(ahci, ahci_cfg_registers[i].addr),
+ ahci_cfg_registers[i].name);
+ break;
+ }
+ }
+
+ printf("\n============= SATA Initialization Registers ==============\n\n");
+ for (i = 0; i < ahci_sir_registers_size; i++) {
+ pci_write_byte(ahci, ahci_sir_offset, ahci_sir_registers[i].addr);
+ switch (ahci_sir_registers[i].size) {
+ case 4:
+ printf("0x%02x: 0x%08x (%s)\n",
+ ahci_sir_registers[i].addr,
+ pci_read_long(ahci, ahci_sir_offset),
+ ahci_sir_registers[i].name);
+ break;
+ case 2:
+ printf("0x%02x: 0x%04x (%s)\n",
+ ahci_sir_registers[i].addr,
+ pci_read_word(ahci, ahci_sir_offset),
+ ahci_sir_registers[i].name);
+ break;
+ case 1:
+ printf("0x%02x: 0x%02x (%s)\n",
+ ahci_sir_registers[i].addr,
+ pci_read_byte(ahci, ahci_sir_offset),
+ ahci_sir_registers[i].name);
+ break;
+ }
+ }
+
const pciaddr_t ahci_phys = ahci->base_addr[5] & ~0x7ULL;
printf("\n============= ABAR ==============\n\n");
printf("ABAR = 0x%08llx (MEM)\n\n", (unsigned long long)ahci_phys);