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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-07-20 12:50:20 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-07-22 05:39:39 +0200
commiteb61ea84f7226d6c081441bbb6fbafbb920505db (patch)
tree95026f44c1a6830c5d22c6020c4011192f10c612
parent9ec691429f1d851c08297d65ff56729fccc6397c (diff)
downloadcoreboot-eb61ea84f7226d6c081441bbb6fbafbb920505db.tar.xz
intel car: Unify whitespace and comment fixes
Change-Id: Icd0cc7d27f38bdaee6addb98abec6f310cdd9fae Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15759 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r--src/cpu/intel/car/cache_as_ram_ht.inc2
-rw-r--r--src/cpu/intel/haswell/cache_as_ram.inc11
-rw-r--r--src/cpu/intel/model_2065x/cache_as_ram.inc8
-rw-r--r--src/cpu/intel/model_206ax/cache_as_ram.inc8
-rw-r--r--src/cpu/intel/model_6ex/cache_as_ram.inc2
5 files changed, 15 insertions, 16 deletions
diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc
index 84a55c738a..0abda49f90 100644
--- a/src/cpu/intel/car/cache_as_ram_ht.inc
+++ b/src/cpu/intel/car/cache_as_ram_ht.inc
@@ -288,7 +288,7 @@ no_msr_11e:
invd
movl %eax, %cr0
- /* Clear the cache memory reagion. */
+ /* Clear the cache memory region. This will also fill up the cache. */
cld
xorl %eax, %eax
movl $CACHE_AS_RAM_BASE, %edi
diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc
index 2ccef786fa..3349883c53 100644
--- a/src/cpu/intel/haswell/cache_as_ram.inc
+++ b/src/cpu/intel/haswell/cache_as_ram.inc
@@ -30,8 +30,7 @@
#define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES)
#define CACHE_MRC_MASK (~CACHE_MRC_BYTES)
-#define CPU_MAXPHYSADDR CONFIG_CPU_ADDR_BITS
-#define CPU_PHYSMASK_HI (1 << (CPU_MAXPHYSADDR - 32) - 1)
+#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
#define NoEvictMod_MSR 0x2e0
@@ -96,7 +95,7 @@ clear_mtrrs:
wrmsr
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
- movl %cr0, %eax
+ movl %cr0, %eax
andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
invd
movl %eax, %cr0
@@ -108,7 +107,7 @@ clear_mtrrs:
andl $~2, %eax
wrmsr
- /* Clear the cache memory region. This will also fill up the cache */
+ /* Clear the cache memory region. This will also fill up the cache. */
movl $CACHE_AS_RAM_BASE, %esi
movl %esi, %edi
movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
@@ -135,8 +134,8 @@ clear_mtrrs:
* IMPORTANT: The following calculation _must_ be done at runtime. See
* http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
- movl $copy_and_run, %eax
- andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
+ movl $copy_and_run, %eax
+ andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRPROT, %eax
wrmsr
diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc
index e6d95d572a..093c78457d 100644
--- a/src/cpu/intel/model_2065x/cache_as_ram.inc
+++ b/src/cpu/intel/model_2065x/cache_as_ram.inc
@@ -101,7 +101,7 @@ clear_var_mtrrs:
wrmsr
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
- movl %cr0, %eax
+ movl %cr0, %eax
andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
invd
movl %eax, %cr0
@@ -113,7 +113,7 @@ clear_var_mtrrs:
andl $~2, %eax
wrmsr
- /* Clear the cache memory region. This will also fill up the cache */
+ /* Clear the cache memory region. This will also fill up the cache. */
movl $CACHE_AS_RAM_BASE, %esi
movl %esi, %edi
movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
@@ -140,8 +140,8 @@ clear_var_mtrrs:
* IMPORTANT: The following calculation _must_ be done at runtime. See
* http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
- movl $copy_and_run, %eax
- andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
+ movl $copy_and_run, %eax
+ andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRPROT, %eax
wrmsr
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc
index a1f5cc9d80..2757c552cb 100644
--- a/src/cpu/intel/model_206ax/cache_as_ram.inc
+++ b/src/cpu/intel/model_206ax/cache_as_ram.inc
@@ -93,7 +93,7 @@ clear_mtrrs:
wrmsr
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
- movl %cr0, %eax
+ movl %cr0, %eax
andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
invd
movl %eax, %cr0
@@ -105,7 +105,7 @@ clear_mtrrs:
andl $~2, %eax
wrmsr
- /* Clear the cache memory region. This will also fill up the cache */
+ /* Clear the cache memory region. This will also fill up the cache. */
movl $CACHE_AS_RAM_BASE, %esi
movl %esi, %edi
movl $(CACHE_AS_RAM_SIZE >> 2), %ecx
@@ -132,8 +132,8 @@ clear_mtrrs:
* IMPORTANT: The following calculation _must_ be done at runtime. See
* http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
*/
- movl $copy_and_run, %eax
- andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
+ movl $copy_and_run, %eax
+ andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
orl $MTRR_TYPE_WRPROT, %eax
wrmsr
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc
index edd9e6c961..9ae217c9e9 100644
--- a/src/cpu/intel/model_6ex/cache_as_ram.inc
+++ b/src/cpu/intel/model_6ex/cache_as_ram.inc
@@ -83,7 +83,7 @@ clear_mtrrs:
invd
movl %eax, %cr0
- /* Clear the cache memory reagion. */
+ /* Clear the cache memory region. This will also fill up the cache. */
movl $CACHE_AS_RAM_BASE, %esi
movl %esi, %edi
movl $(CACHE_AS_RAM_SIZE >> 2), %ecx