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authorDuncan Laurie <dlaurie@chromium.org>2014-06-10 10:03:22 -0700
committerMarc Jones <marc.jones@se-eng.com>2015-01-04 00:05:23 +0100
commitef57a22163519431dc0951f2ccc857f1027d7109 (patch)
tree14ae25feba2832dd287492a236147a338466df15
parent502c38f9df25bfaf650271d93ea90069a1d0ccd6 (diff)
downloadcoreboot-ef57a22163519431dc0951f2ccc857f1027d7109.tar.xz
wtm2: Fix issues with USB in firmware
XHCI driver was not enabled in libpayload and some ports were disabled that should be enabled. The Chrome OS GPIOs also need to be reported as 0xFFFFFFFF to properly indicate unused so crossystem does not attempt to export GPIO number 255 in the kernel and trigger a warning. BUG=chrome-os-partner:28234 TEST=Build and boot on wtm2 Original-Change-Id: Ib5727ef6e618c959640b200757cfa13f95c7cb0f Original-CSigned-off-by: Duncan Laurie <dlaurie@chromium.org> Original-CReviewed-on: https://chromium-review.googlesource.com/203184 Original-CReviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 328362469b00c9467908a7d18a031fee73753def) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I91ef865c44d3c73b0d74c9eaf1fbf2fb5e894434 Reviewed-on: http://review.coreboot.org/8047 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
-rw-r--r--src/mainboard/intel/wtm2/acpi/chromeos.asl6
-rw-r--r--src/mainboard/intel/wtm2/pei_data.c6
2 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/intel/wtm2/acpi/chromeos.asl b/src/mainboard/intel/wtm2/acpi/chromeos.asl
index 40ffcf0156..4cd6dedf46 100644
--- a/src/mainboard/intel/wtm2/acpi/chromeos.asl
+++ b/src/mainboard/intel/wtm2/acpi/chromeos.asl
@@ -18,7 +18,7 @@
*/
Name(OIPG, Package() {
- Package () { 0x0001, 0, 0xFF, "LynxPoint" }, // recovery
- Package () { 0x0002, 0, 0xFF, "LynxPoint" }, // developer
- Package () { 0x0003, 0, 0xFF, "LynxPoint" }, // firmware write protect
+ Package () { 0x0001, 0, 0xFFFFFFFF, "PCH-LP" }, // recovery
+ Package () { 0x0002, 0, 0xFFFFFFFF, "PCH-LP" }, // developer
+ Package () { 0x0003, 0, 0xFFFFFFFF, "PCH-LP" }, // firmware write protect
})
diff --git a/src/mainboard/intel/wtm2/pei_data.c b/src/mainboard/intel/wtm2/pei_data.c
index a33dddfe30..e67d8e58ef 100644
--- a/src/mainboard/intel/wtm2/pei_data.c
+++ b/src/mainboard/intel/wtm2/pei_data.c
@@ -47,11 +47,11 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
USB_PORT_FRONT_PANEL);
pei_data_usb2_port(pei_data, 6, 0x40, 1, USB_OC_PIN_SKIP,
USB_PORT_FRONT_PANEL);
- pei_data_usb2_port(pei_data, 7, 0x40, 0, USB_OC_PIN_SKIP,
+ pei_data_usb2_port(pei_data, 7, 0x40, 1, USB_OC_PIN_SKIP,
USB_PORT_FRONT_PANEL);
pei_data_usb3_port(pei_data, 0, 1, USB_OC_PIN_SKIP, 0);
pei_data_usb3_port(pei_data, 1, 1, USB_OC_PIN_SKIP, 0);
- pei_data_usb3_port(pei_data, 2, 0, USB_OC_PIN_SKIP, 0);
- pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0);
+ pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0);
+ pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0);
}