soc/intel/broadwell: Drop `gpu_panel_port_select`

The corresponding bits in PP_ON_DELAYS are reserved MBZ.

Change-Id: I9789a7d50c4bce2ccad0bf476f877db25e3ff82e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

9 files changed, 7 insertions, 16 deletions

diff --git a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb
index 70b1ebd552..60aef30a58 100644
--- a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb
+++ b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb
@@ -1,7 +1,6 @@
 chip soc/intel/broadwell
 
-	# Enable Panel and configure power delays
-	register "gpu_panel_port_select" = "1"			# eDP
+	# Set panel power delays
 	register "gpu_panel_power_cycle_delay" = "5"		# 400ms
 	register "gpu_panel_power_up_delay" = "400"		# 40ms
 	register "gpu_panel_power_down_delay" = "150"		# 15ms
diff --git a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb
index 67b9131c65..da80fecba8 100644
--- a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb
+++ b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb
@@ -1,7 +1,6 @@
 chip soc/intel/broadwell
 
-	# Enable Panel and configure power delays
-	register "gpu_panel_port_select" = "1"			# eDP
+	# Set panel power delays
 	register "gpu_panel_power_cycle_delay" = "5"		# 400ms
 	register "gpu_panel_power_up_delay" = "400"		# 40ms
 	register "gpu_panel_power_down_delay" = "150"		# 15ms
diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb
index f814280b15..f14896425a 100644
--- a/src/mainboard/google/auron/variants/buddy/overridetree.cb
+++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb
@@ -1,7 +1,6 @@
 chip soc/intel/broadwell
 
-	# Enable Panel and configure power delays
-	register "gpu_panel_port_select" = "1"			# eDP
+	# Set panel power delays
 	register "gpu_panel_power_cycle_delay" = "5"		# 400ms
 	register "gpu_panel_power_up_delay" = "400"		# 40ms
 	register "gpu_panel_power_down_delay" = "150"		# 15ms
diff --git a/src/mainboard/google/auron/variants/gandof/overridetree.cb b/src/mainboard/google/auron/variants/gandof/overridetree.cb
index e35d3a5529..75c202d663 100644
--- a/src/mainboard/google/auron/variants/gandof/overridetree.cb
+++ b/src/mainboard/google/auron/variants/gandof/overridetree.cb
@@ -1,7 +1,6 @@
 chip soc/intel/broadwell
 
-	# Enable Panel and configure power delays
-	register "gpu_panel_port_select" = "1"			# eDP
+	# Set panel power delays
 	register "gpu_panel_power_cycle_delay" = "5"		# 400ms
 	register "gpu_panel_power_up_delay" = "400"		# 40ms
 	register "gpu_panel_power_down_delay" = "150"		# 15ms
diff --git a/src/mainboard/google/auron/variants/lulu/overridetree.cb b/src/mainboard/google/auron/variants/lulu/overridetree.cb
index 70b1ebd552..60aef30a58 100644
--- a/src/mainboard/google/auron/variants/lulu/overridetree.cb
+++ b/src/mainboard/google/auron/variants/lulu/overridetree.cb
@@ -1,7 +1,6 @@
 chip soc/intel/broadwell
 
-	# Enable Panel and configure power delays
-	register "gpu_panel_port_select" = "1"			# eDP
+	# Set panel power delays
 	register "gpu_panel_power_cycle_delay" = "5"		# 400ms
 	register "gpu_panel_power_up_delay" = "400"		# 40ms
 	register "gpu_panel_power_down_delay" = "150"		# 15ms
diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb
index 93e96cac3f..c5d27476c7 100644
--- a/src/mainboard/google/auron/variants/samus/overridetree.cb
+++ b/src/mainboard/google/auron/variants/samus/overridetree.cb
@@ -3,8 +3,7 @@ chip soc/intel/broadwell
 	# Enable DDI2 Hotplug with 6ms pulse
 	register "gpu_dp_c_hotplug" = "0x06"
 
-	# Enable Panel and configure power delays
-	register "gpu_panel_port_select" = "1"			# eDP
+	# Set panel power delays
 	register "gpu_panel_power_cycle_delay" = "6"		# 500ms
 	register "gpu_panel_power_up_delay" = "2000"		# 200ms
 	register "gpu_panel_power_down_delay" = "500"		# 50ms
diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb
index 0d44cd734f..b7c6fe58ae 100644
--- a/src/mainboard/purism/librem_bdw/devicetree.cb
+++ b/src/mainboard/purism/librem_bdw/devicetree.cb
@@ -9,8 +9,7 @@ chip soc/intel/broadwell
 	# Set backlight PWM value for eDP
 	register "gpu_pch_backlight_pwm_hz" = "200"
 
-	# Enable Panel and configure power delays
-	register "gpu_panel_port_select" = "1"			# eDP
+	# Set panel power delays
 	register "gpu_panel_power_cycle_delay" = "6"		# 500ms
 	register "gpu_panel_power_up_delay" = "2000"		# 200ms
 	register "gpu_panel_power_down_delay" = "500"		# 50ms
diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h
index 554399823a..f559410c57 100644
--- a/src/soc/intel/broadwell/chip.h
+++ b/src/soc/intel/broadwell/chip.h
@@ -84,7 +84,6 @@ struct soc_intel_broadwell_config {
 	u8 gpu_dp_d_hotplug;
 
 	/* Panel power sequence timings */
-	u8 gpu_panel_port_select;
 	u8 gpu_panel_power_cycle_delay;
 	u16 gpu_panel_power_up_delay;
 	u16 gpu_panel_power_down_delay;
diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c
index 41167b1cf9..ba453cdb27 100644
--- a/src/soc/intel/broadwell/igd.c
+++ b/src/soc/intel/broadwell/igd.c
@@ -298,7 +298,6 @@ static void igd_setup_panel(struct device *dev)
 	/* Setup Panel Power On Delays */
 	reg32 = gtt_read(PCH_PP_ON_DELAYS);
 	if (!reg32) {
-		reg32 = (conf->gpu_panel_port_select & 0x3) << 30;
 		reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16;
 		reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff);
 		gtt_write(PCH_PP_ON_DELAYS, reg32);