summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorJamie Ryu <jamie.m.ryu@intel.com>2020-06-11 01:57:13 -0700
committerNick Vaccaro <nvaccaro@google.com>2020-07-03 23:56:34 +0000
commit02a1b338f833e095191b78aef8763ba361fee489 (patch)
treedfe55a7158e8959a4ce0843873387e05378239e4
parent401671c7abff10f4658d9418c2a0553da82b5197 (diff)
downloadcoreboot-02a1b338f833e095191b78aef8763ba361fee489.tar.xz
soc/intel/tigerlake: Disable hybrid storage mode in CSE Lite RO boot
A UPD HybridStorageMode allows a platform to dynamically configure the PCIe strap configuration required if an Optane device is connected. The strap configuration is done by HECI commands between FSP and CSE to override the default PCIe strap value, and the updated strap value is stored in SPI RW data to be used on the next boot. CSE Lite supports the strap override when running on CSE RW partition, while CSE RO partition does not support it because CSE RO is not allowed to access SPI RW data. The strap override failure on CSE RO causes FSP not initializing PCH Clkreq and PCIe port mapping and this results NVMe and Optane initialization failure. By disabling HybridStorageMode in case of CSE RO boot, NVMe detection is done by the default PCIe configuration and Optane is detected as a single NVMe storage device on CSE RO boot in recovery mode. Both NVMe and Optane devices detection as well as OS installation to these storage devices are verified on CSE RO boot in recovery mode. BUG=b:158643194 TEST=boot and verified with tglrvp and volteer in recovery mode Cq-Depend: chrome-internal:3100721 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: I5397cfc007069debe3701bf1e38e81bd17a29f0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/42282 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/intel/tigerlake/fsp_params.c16
1 files changed, 15 insertions, 1 deletions
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index a612427418..3187a33eaf 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -7,9 +7,11 @@
#include <fsp/api.h>
#include <fsp/ppi/mp_service_ppi.h>
#include <fsp/util.h>
+#include <intelblocks/cse.h>
#include <intelblocks/lpss.h>
#include <intelblocks/xdci.h>
#include <intelpch/lockdown.h>
+#include <security/vboot/vboot_common.h>
#include <soc/gpio_soc_defs.h>
#include <soc/intel/common/vbt.h>
#include <soc/pci_devs.h>
@@ -255,7 +257,19 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER;
/* Enable Hybrid storage auto detection */
- params->HybridStorageMode = config->HybridStorageMode;
+ if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && cse_is_hfs3_fw_sku_lite()
+ && vboot_recovery_mode_enabled() && !cse_is_hfs1_com_normal()) {
+ /*
+ * CSE Lite SKU does not support hybrid storage dynamic configuration
+ * in CSE RO boot, and FSP does not allow to send the strap override
+ * HECI commands if CSE is not in normal mode; hence, hybrid storage
+ * mode is disabled on CSE RO boot in recovery boot mode.
+ */
+ printk(BIOS_INFO, "cse_lite: CSE RO boot. HybridStorageMode disabled\n");
+ params->HybridStorageMode = 0;
+ } else {
+ params->HybridStorageMode = config->HybridStorageMode;
+ }
/* USB4/TBT */
for (i = 0; i < ARRAY_SIZE(params->ITbtPcieRootPortEn); i++) {