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authorMartin Roth <martin@coreboot.org>2020-07-08 16:19:37 -0600
committerMartin Roth <martinroth@google.com>2020-07-09 00:26:05 +0000
commit037ee4b5562099771795d52cf7149ddff8dd3595 (patch)
tree995ae6ab809ee40482132a11acfc28091c804d92
parent85dcd2f1ea2cc140f1bbd724d32db532d4908a44 (diff)
downloadcoreboot-037ee4b5562099771795d52cf7149ddff8dd3595.tar.xz
soc/amd/picasso: Add dummy spinlock for psp_verstage
If CONFIG_CMOS_POST is enabled, psp_verstage breaks because the spinlock code is missing. Add dummy spinlock code as the spinlocks aren't needed in the PSP. TEST=Build with CONFIG_CMOS_POST enabled. BUG=None Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Iea6f31e500e1b26f0b974c6eaa486209b9c81459 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43310 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/amd/picasso/psp_verstage/include/arch/smp/spinlock.h17
1 files changed, 17 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/psp_verstage/include/arch/smp/spinlock.h b/src/soc/amd/picasso/psp_verstage/include/arch/smp/spinlock.h
new file mode 100644
index 0000000000..5245bd1a02
--- /dev/null
+++ b/src/soc/amd/picasso/psp_verstage/include/arch/smp/spinlock.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _ARCH_SMP_SPINLOCK_H
+#define _ARCH_SMP_SPINLOCK_H
+
+#define DECLARE_SPIN_LOCK(x)
+#define barrier() do {} while (0)
+#define spin_is_locked(lock) 0
+#define spin_unlock_wait(lock) do {} while (0)
+#define spin_lock(lock) do {} while (0)
+#define spin_unlock(lock) do {} while (0)
+#define cpu_relax() do {} while (0)
+
+#include <smp/node.h>
+#define boot_cpu() 1
+
+#endif