diff options
| author | Shaunak Saha <shaunak.saha@intel.com> | 2016-07-11 16:03:52 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-07-13 23:36:34 +0200 |
| commit | 0cf11cb7837d34589da466dcdcfa0aecc1e6c3db (patch) | |
| tree | 2f59435e55ce2d914f09a093358998a1d9a89a4c | |
| parent | 81d1e09113bc12ea9427e9522d4f5eab982c145e (diff) | |
| download | coreboot-0cf11cb7837d34589da466dcdcfa0aecc1e6c3db.tar.xz | |
soc/intel/apollolake: add offset of GPIO_TIER1_SCI_EN bit
This patch adds the support for gpio_tier1_sci_en bit which
needs to be set before going to sleep so that when
gpio_tier1_sci_sts bit gets set platform can wake
from S3.
BUG = chrome-os-partner:53992
TEST = Platform wakes from S3 on lidopen,key press.
Tested on Amenia and Reef boards.
Change-Id: I3ba79fa53ca8817149d585fa795a8f427c128dcb
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/15612
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/pm.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 99f922f244..b0e2da21ce 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -119,6 +119,11 @@ #define GPE0_STS(x) (0x20 + (x * 4)) #define GPE0_EN(x) (0x30 + (x * 4)) #define PME_B0_EN (1 << 13) +/* + * Enables the setting of the GPIO_TIER1_SCI_STS bit to generate a wake event + * and/or an SCI or SMI#. + */ +#define GPIO_TIER_1_SCI (1 << 15) /* Memory mapped IO registers behind PMC_BASE_ADDRESS */ #define PRSTS 0x1000 |