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authorAlexey Buyanov <alexey.buyanov@intel.com>2020-07-28 19:59:45 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-08-26 07:36:21 +0000
commit12016969c50a34b7385ca435554be9670d031ea4 (patch)
tree1295e67db8b3aa2f17593b03a1000ec786c78e97
parent85a44639768e8365ba5e34e6752c7481534797b9 (diff)
downloadcoreboot-12016969c50a34b7385ca435554be9670d031ea4.tar.xz
soc/intel/tigerlake: Rename pch_init() code
Rename the pch_init function to bootblock_pch_init and romstage_pch_init according to the stage it is defined in. TEST=successfully built and booted TGLRVP Signed-off-by: Alexey Buyanov <alexey.buyanov@intel.com> Change-Id: Ib7450fcdc3024dfb5e375a54f9bdcdca9bc373d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
-rw-r--r--src/soc/intel/tigerlake/bootblock/bootblock.c2
-rw-r--r--src/soc/intel/tigerlake/bootblock/pch.c2
-rw-r--r--src/soc/intel/tigerlake/include/soc/bootblock.h2
-rw-r--r--src/soc/intel/tigerlake/include/soc/romstage.h2
-rw-r--r--src/soc/intel/tigerlake/romstage/pch.c2
-rw-r--r--src/soc/intel/tigerlake/romstage/romstage.c2
6 files changed, 6 insertions, 6 deletions
diff --git a/src/soc/intel/tigerlake/bootblock/bootblock.c b/src/soc/intel/tigerlake/bootblock/bootblock.c
index e7d97c50bf..96e6268f74 100644
--- a/src/soc/intel/tigerlake/bootblock/bootblock.c
+++ b/src/soc/intel/tigerlake/bootblock/bootblock.c
@@ -25,7 +25,7 @@ void bootblock_soc_early_init(void)
void bootblock_soc_init(void)
{
report_platform_info();
- pch_init();
+ bootblock_pch_init();
/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
tco_configure();
diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c
index 63beeaa601..18ca5e51af 100644
--- a/src/soc/intel/tigerlake/bootblock/pch.c
+++ b/src/soc/intel/tigerlake/bootblock/pch.c
@@ -141,7 +141,7 @@ void pch_early_iorange_init(void)
pch_enable_lpc();
}
-void pch_init(void)
+void bootblock_pch_init(void)
{
/*
* Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,
diff --git a/src/soc/intel/tigerlake/include/soc/bootblock.h b/src/soc/intel/tigerlake/include/soc/bootblock.h
index 783009b693..87be0e0a70 100644
--- a/src/soc/intel/tigerlake/include/soc/bootblock.h
+++ b/src/soc/intel/tigerlake/include/soc/bootblock.h
@@ -8,7 +8,7 @@ void bootblock_cpu_init(void);
void bootblock_pch_early_init(void);
/* Bootblock post console init programming */
-void pch_init(void);
+void bootblock_pch_init(void);
void pch_early_iorange_init(void);
void report_platform_info(void);
diff --git a/src/soc/intel/tigerlake/include/soc/romstage.h b/src/soc/intel/tigerlake/include/soc/romstage.h
index bd6096b7a3..baa35c5216 100644
--- a/src/soc/intel/tigerlake/include/soc/romstage.h
+++ b/src/soc/intel/tigerlake/include/soc/romstage.h
@@ -9,7 +9,7 @@
bool mainboard_get_dram_part_num(const char **part_num, size_t *len);
void mainboard_memory_init_params(FSPM_UPD *mupd);
void systemagent_early_init(void);
-void pch_init(void);
+void romstage_pch_init(void);
/* Board type */
enum board_type {
diff --git a/src/soc/intel/tigerlake/romstage/pch.c b/src/soc/intel/tigerlake/romstage/pch.c
index 9fd8a1e43e..d3c2554425 100644
--- a/src/soc/intel/tigerlake/romstage/pch.c
+++ b/src/soc/intel/tigerlake/romstage/pch.c
@@ -3,7 +3,7 @@
#include <intelblocks/smbus.h>
#include <soc/romstage.h>
-void pch_init(void)
+void romstage_pch_init(void)
{
/* Program SMBUS_BASE_ADDRESS and Enable it */
smbus_common_init();
diff --git a/src/soc/intel/tigerlake/romstage/romstage.c b/src/soc/intel/tigerlake/romstage/romstage.c
index 54632383eb..db014ea5d6 100644
--- a/src/soc/intel/tigerlake/romstage/romstage.c
+++ b/src/soc/intel/tigerlake/romstage/romstage.c
@@ -131,7 +131,7 @@ void mainboard_romstage_entry(void)
/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
systemagent_early_init();
/* Program PCH init */
- pch_init();
+ romstage_pch_init();
/* initialize Heci interface */
heci_init(HECI1_BASE_ADDRESS);