exynos5420/pit: re-factor membaseconfig0/1 usage

membaseconfig0/1 are utterly dependent on the mainboard's particular
DRAM setup. This defines their values in the mem_timings struct for
pit.

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Old-Change-Id: Ifd782d1229b2418f8ddbf0bcb3f45cc828ac34b0
Reviewed-on: https://chromium-review.googlesource.com/167488
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: ron minnich <rminnich@chromium.org>
(cherry picked from commit 80eebd5bc0dbb9fabf81f46c25dcd5c5d5747579)

exynos5420: necessary updates for DRAM

This updates DRAM usage for Exynos5420 so that we can actually
use 3.5GB:

- Memory chips used with Exynos5420 may have 16 row address lines.

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Old-Change-Id: I86d1a96d0d1a028587f7655f8de5a2e52165e9d2
Reviewed-on: https://chromium-review.googlesource.com/167489
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: ron minnich <rminnich@chromium.org>
(cherry picked from commit 04bbaf5d8e125166dd689f656d5b37776be01fb1)

Squashed two related commits.

Change-Id: I4e45bc8a446715897ec21b0160701152fa6b226b
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6613
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

3 files changed, 23 insertions, 24 deletions

diff --git a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c
index 1126dca130..1d7b8a8adb 100644
--- a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c
+++ b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c
@@ -145,21 +145,15 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
 	update_reset_dll(drex0, DDR_MODE_DDR3);
 	update_reset_dll(drex1, DDR_MODE_DDR3);
 
-	/* Set Base Address:
-	 * 0x2000_0000 ~ 0x5FFF_FFFF
-	 * 0x6000_0000 ~ 0x9FFF_FFFF
-	 */
-	/* MEMBASECONFIG0 */
-	val = DMC_MEMBASECONFIGx_CHIP_BASE(DMC_CHIP_BASE_0) |
-		DMC_MEMBASECONFIGx_CHIP_MASK(DMC_CHIP_MASK);
-	writel(val, &tzasc0->membaseconfig0);
-	writel(val, &tzasc1->membaseconfig0);
-
-	/* MEMBASECONFIG1 */
-	val = DMC_MEMBASECONFIGx_CHIP_BASE(DMC_CHIP_BASE_1) |
-		DMC_MEMBASECONFIGx_CHIP_MASK(DMC_CHIP_MASK);
-	writel(val, &tzasc0->membaseconfig1);
-	writel(val, &tzasc1->membaseconfig1);
+	/* MEMBASECONFIG0 (CS0) */
+	writel(mem->membaseconfig0, &tzasc0->membaseconfig0);
+	writel(mem->membaseconfig0, &tzasc1->membaseconfig0);
+
+	/* MEMBASECONFIG1 (CS1) */
+	if (mem->chips_per_channel == 2) {
+		writel(mem->membaseconfig1, &tzasc0->membaseconfig1);
+		writel(mem->membaseconfig1, &tzasc1->membaseconfig1);
+	}
 
 	/* Memory Channel Inteleaving Size
 	 * Exynos5420 Channel interleaving = 128 bytes
diff --git a/src/cpu/samsung/exynos5420/setup.h b/src/cpu/samsung/exynos5420/setup.h
index 3bd36b2e75..950c2c6f85 100644
--- a/src/cpu/samsung/exynos5420/setup.h
+++ b/src/cpu/samsung/exynos5420/setup.h
@@ -136,6 +136,7 @@ struct exynos5_phy_control;
 #define DMC_MEMCONFIGx_CHIP_COL_10              (3 << 8)
 #define DMC_MEMCONFIGx_CHIP_ROW_14              (2 << 4)
 #define DMC_MEMCONFIGx_CHIP_ROW_15              (3 << 4)
+#define DMC_MEMCONFIGx_CHIP_ROW_16              (4 << 4)
 #define DMC_MEMCONFIGx_CHIP_BANK_8              (3 << 0)
 
 #define DMC_MEMBASECONFIGx_CHIP_BASE(x)         (x << 16)
@@ -767,15 +768,12 @@ struct exynos5_phy_control;
 #define DPWRDN_EN		(1 << 1)
 #define DSREF_EN		(1 << 5)
 
-/* As we use channel interleaving, therefore value of the base address
- * register must be set as half of the bus base address
- * RAM start addess is 0x2000_0000 which means chip_base is 0x20, so
- * we need to set half 0x10 to the membaseconfigx registers
- * see exynos5420 UM section 17.17.3.21 for more
- */
-#define DMC_CHIP_BASE_0 0x10
-#define DMC_CHIP_BASE_1 0x50
-#define DMC_CHIP_MASK	0x7C0
+/* AXI base address mask */
+#define DMC_CHIP_MASK_256MB	0x7f0
+#define DMC_CHIP_MASK_512MB	0x7e0
+#define DMC_CHIP_MASK_1GB	0x7c0
+#define DMC_CHIP_MASK_2GB	0x780
+#define DMC_CHIP_MASK_4GB	0x700
 
 #define MEMBASECONFIG_CHIP_MASK_VAL	0x7E0
 #define MEMBASECONFIG_CHIP_MASK_OFFSET	0
diff --git a/src/mainboard/google/pit/memory.c b/src/mainboard/google/pit/memory.c
index 4ac3d0c999..0c30773bdd 100644
--- a/src/mainboard/google/pit/memory.c
+++ b/src/mainboard/google/pit/memory.c
@@ -90,6 +90,13 @@ const struct mem_timings mem_timings = {
 			DMC_MEMCONTROL_BL_8 |
 			DMC_MEMCONTROL_PZQ_DISABLE |
 			DMC_MEMCONTROL_MRR_BYTE_7_0,
+		/*
+		 * For channel interleaving, the chip_base needs to be set to
+		 * half the bus address. So for a base address of 0x2000_0000,
+		 * the chip_base value is 0x20 without interleaving and 0x10
+		 * with channel interleaving. See note in section 17.14.
+		 */
+		.membaseconfig0 = (0x10 << 16) | DMC_CHIP_MASK_1GB,
 		.memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT |
 			DMC_MEMCONFIGx_CHIP_COL_10 |
 			DMC_MEMCONFIGx_CHIP_ROW_15 |