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authorMartin Roth <martinroth@google.com>2015-11-12 14:02:42 -0700
committerMartin Roth <martinroth@google.com>2015-11-19 00:16:50 +0100
commit1455437c9e010bcc617c5927e18cf1cb3b02c82f (patch)
tree090b6d94cdd166d4302aa0053c8d37cfb19de642
parentae16c4034c37a28e352936d0600b51be21340524 (diff)
downloadcoreboot-1455437c9e010bcc617c5927e18cf1cb3b02c82f.tar.xz
x86: Add Kconfig to disable early bootblock postcodes
The Intel cave creek chipset needs to have port 80 routing configured before any post codes can be sent to port 80h. Sending post codes out before the routing is done will hang the system. This patch allows us to disable the first couple of post codes that go out before the routing can be configured. The Kconfig symbol is selected by the cave creek chipset (fsp_i89xx). Change-Id: I9bf41669ec32744f87a1ed2de011d31c72ea38da Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12422 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: York Yang <york.yang@intel.com>
-rw-r--r--src/console/Kconfig9
-rw-r--r--src/cpu/x86/16bit/entry16.inc3
-rw-r--r--src/cpu/x86/32bit/entry32.inc2
-rw-r--r--src/southbridge/intel/fsp_i89xx/Kconfig1
4 files changed, 14 insertions, 1 deletions
diff --git a/src/console/Kconfig b/src/console/Kconfig
index a2f893a6fc..d81563794b 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -350,4 +350,13 @@ config POST_IO_PORT
depending on the presence of coprocessors/microcontrollers or if the
platform does not support IO in the conventional x86 manner.
+config NO_EARLY_BOOTBLOCK_POSTCODES
+ def_bool n
+ help
+ Some chipsets require that the routing for the port 80h POST
+ code be configured before any POST codes are sent out.
+ This can be done in the boot block, but there are a couple of
+ POST codes that go out before the chipset's bootblock initialization
+ can happen. This option suppresses those POST codes.
+
endmenu
diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc
index 4dad1e5a7b..abaf6718ea 100644
--- a/src/cpu/x86/16bit/entry16.inc
+++ b/src/cpu/x86/16bit/entry16.inc
@@ -36,8 +36,9 @@ _start:
cli
/* Save the BIST result */
movl %eax, %ebp
-
+#if !IS_ENABLED(CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES)
post_code(POST_RESET_VECTOR_CORRECT)
+#endif
/* IMMEDIATELY invalidate the translation lookaside buffer (TLB) before
* executing any further code. Even though paging is disabled we
diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc
index 5c3072e8dc..9ef3bc1c6e 100644
--- a/src/cpu/x86/32bit/entry32.inc
+++ b/src/cpu/x86/32bit/entry32.inc
@@ -56,7 +56,9 @@ __protected_start:
/* Save the BIST value */
movl %eax, %ebp
+#if !IS_ENABLED(CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES)
post_code(POST_ENTER_PROTECTED_MODE)
+#endif
movw $ROM_DATA_SEG, %ax
movw %ax, %ds
diff --git a/src/southbridge/intel/fsp_i89xx/Kconfig b/src/southbridge/intel/fsp_i89xx/Kconfig
index d1426d670b..9d195d2647 100644
--- a/src/southbridge/intel/fsp_i89xx/Kconfig
+++ b/src/southbridge/intel/fsp_i89xx/Kconfig
@@ -34,6 +34,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select SPI_FLASH
select COMMON_FADT
select HAVE_INTEL_FIRMWARE
+ select NO_EARLY_BOOTBLOCK_POSTCODES
config EHCI_BAR
hex