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| author | Zheng Bao <zheng.bao@amd.com> | 2009-08-25 04:12:55 +0000 |
|---|---|---|
| committer | Zheng Bao <Zheng.Bao@amd.com> | 2009-08-25 04:12:55 +0000 |
| commit | 1476a9ecc410ab1c8443332fc8e71fc5d16442e1 (patch) | |
| tree | 836720358425cbbe96f79eb22fe295c921d2b455 | |
| parent | 4d7ae4d96ee0b3d902034bc6878a84fbfa0d45fb (diff) | |
| download | coreboot-1476a9ecc410ab1c8443332fc8e71fc5d16442e1.tar.xz | |
Without this patch, if we only got a DIMM in Channel B, memory can not be
set up correctly. Now it can. Please test it.
Moving "mct_AfterGetCLT(pMCTstat, pDCTstat, dct);" out of the "if" is the
key point.
Changing the Get_DIMMAddress_D(pDCTstat, i) to Get_DIMMAddress_D(pDCTstat, dct + i)
doesnt seem to take any effect. But I believe this is what it should be.
And a duplicated semicolon is removed.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4569 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
| -rw-r--r-- | src/northbridge/amd/amdmct/mct/mct_d.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 105ae662b8..1a10cafd60 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -352,7 +352,7 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat, nv_DQSTrainCTL = 1; print_t("DQSTiming_D: mct_BeforeDQSTrain_D:\n"); - mct_BeforeDQSTrain_D(pMCTstat, pDCTstatA);; + mct_BeforeDQSTrain_D(pMCTstat, pDCTstatA); phyAssistedMemFnceTraining(pMCTstat, pDCTstatA); if (nv_DQSTrainCTL) { @@ -982,8 +982,8 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat, if ( mctGet_NVbits(NV_MCTUSRTMGMODE) == 2) pDCTstat->Speed = mctGet_NVbits(NV_MemCkVal) + 1; - mct_AfterGetCLT(pMCTstat, pDCTstat, dct); } + mct_AfterGetCLT(pMCTstat, pDCTstat, dct); /* Gather all DIMM mini-max values for cycle timing data */ Rows = 0; @@ -1001,7 +1001,7 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat, for ( i = 0; i< MAX_DIMMS_SUPPORTED; i++) { LDIMM = i >> 1; if (pDCTstat->DIMMValid & (1 << i)) { - smbaddr = Get_DIMMAddress_D(pDCTstat, i); + smbaddr = Get_DIMMAddress_D(pDCTstat, dct + i); byte = mctRead_SPD(smbaddr, SPD_ROWSZ); if (Rows < byte) Rows = byte; /* keep track of largest row sz */ |