diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-07-16 09:37:16 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-07-21 17:19:00 +0000 |
| commit | 152a5e19169564e751a06126a45c71f5fbe68ab2 (patch) | |
| tree | 52ce466493ba65421b12b949ebe3a2ad488e4215 | |
| parent | 5f7b1164c56f36d70813c87e46c540e1e4aa03fc (diff) | |
| download | coreboot-152a5e19169564e751a06126a45c71f5fbe68ab2.tar.xz | |
soc/amd: Move SPI base alignment define into common
The decision to leave the alignment in stoneyridge was driven because
of a spec difference with picasso. AMD has checked the design
materials and has confirmed there was no change.
TEST=Build Grunt successfully
BUG=b:130343127
Change-Id: If3a1d5a41dc175c9733fd09ad28627962646daf9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/lpc.h | 1 | ||||
| -rw-r--r-- | src/soc/amd/picasso/include/soc/southbridge.h | 3 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 3 |
3 files changed, 1 insertions, 6 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index 7b33d7ad11..ab913b2df0 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -114,6 +114,7 @@ #define LPC_WIDEIO2_GENERIC_PORT 0x90 #define SPIROM_BASE_ADDRESS_REGISTER 0xa0 +#define SPI_BASE_ALIGNMENT BIT(6) #define SPI_BASE_RESERVED (BIT(4) | BIT(5)) #define ROUTE_TPM_2_SPI BIT(3) #define SPI_ABORT_ENABLE BIT(2) diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 565ab3084d..6fc37f009a 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -225,9 +225,6 @@ #define SATA_CAPABILITIES_REG 0xfc #define SATA_CAPABILITY_SPM BIT(12) -/* SPI Controller (base address in D14F3xA0) */ -#define SPI_BASE_ALIGNMENT BIT(6) - #define SPI_CNTRL0 0x00 #define SPI_BUSY BIT(31) #define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18)) diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index ad4040759c..07c92a185c 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -254,9 +254,6 @@ #define SATA_CAPABILITIES_REG 0xfc #define SATA_CAPABILITY_SPM BIT(12) -/* SPI Controller (base address in D14F3xA0) */ -#define SPI_BASE_ALIGNMENT BIT(6) - #define SPI_CNTRL0 0x00 #define SPI_BUSY BIT(31) #define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18)) |