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authorElyes HAOUAS <ehaouas@noos.fr>2018-10-31 08:06:12 +0100
committerPatrick Georgi <pgeorgi@google.com>2018-11-05 09:05:51 +0000
commit1a5f1c89d752bf906f7428f96c5ff624a1baba97 (patch)
tree80527bf5c4b6168a59513ee5a1ed7957201d263d
parentd35c7fe1bff55471c62b11d208cf3a71dec30d6d (diff)
downloadcoreboot-1a5f1c89d752bf906f7428f96c5ff624a1baba97.tar.xz
cpu/amd: Use common AMD's MSR
This Phase #2 follows the CL done on Phase #1 (Change-Id: I0236e0960cd) Change-Id: Ia296e1f9073b45c9137d17fbef29ce4fdfabcb7c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29369 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/cpu/amd/car/cache_as_ram.inc8
-rw-r--r--src/cpu/amd/microcode/microcode.c3
-rw-r--r--src/include/cpu/amd/msr.h2
3 files changed, 8 insertions, 5 deletions
diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index 7cbf1dbcbb..e4c2704727 100644
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -415,26 +415,26 @@ fam10_mtrr_setup_complete:
jmp_if_not_fam15h(fam15_car_msr_setup_complete)
/* Disable streaming store (DisSS = 1) */
- mov $0xc0011020, %ecx
+ mov $LS_CFG_MSR, %ecx
rdmsr
bts $28, %eax
wrmsr
/* Disable speculative ITLB reloads (DisSpecTlbRld = 1) */
- mov $0xc0011021, %ecx
+ mov $IC_CFG_MSR, %ecx
rdmsr
bts $9, %eax
wrmsr
/* Disable speculative DTLB reloads (DisSpecTlbRld = 1) and set DisHwPf = 1 */
- mov $0xc0011022, %ecx
+ mov $DC_CFG_MSR, %ecx
rdmsr
bts $4, %eax
bts $13, %eax
wrmsr
/* Disable CR0 combining (CombineCr0Cd = 0) */
- mov $0xc001102b, %ecx
+ mov $BU_CFG3_MSR, %ecx
rdmsr
btr $49-32, %edx
wrmsr
diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c
index 68b6953be8..29a550d529 100644
--- a/src/cpu/amd/microcode/microcode.c
+++ b/src/cpu/amd/microcode/microcode.c
@@ -17,6 +17,7 @@
#include <stdint.h>
#include <console/console.h>
#include <cpu/x86/msr.h>
+#include <cpu/amd/msr.h>
#include <cpu/amd/microcode.h>
#include <cbfs.h>
#include <arch/io.h>
@@ -121,7 +122,7 @@ static void apply_microcode_patch(const struct microcode *m)
msr.hi = 0;
msr.lo = (uint32_t)m;
- wrmsr(0xc0010020, msr);
+ wrmsr(MSR_PATCH_LOADER, msr);
UCODE_DEBUG("patch id to apply = 0x%08x\n", m->patch_id);
diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h
index 46ec70d3c9..5d7b5e4fda 100644
--- a/src/include/cpu/amd/msr.h
+++ b/src/include/cpu/amd/msr.h
@@ -58,6 +58,8 @@
#define PSTATE_3_MSR 0xC0010067
#define PSTATE_4_MSR 0xC0010068
+#define MSR_PATCH_LOADER 0xC0010020
+
#define MSR_COFVID_STS 0xC0010071
#define MSR_CSTATE_ADDRESS 0xC0010073
#define OSVW_ID_Length 0xC0010140