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authorSubrata Banik <subrata.banik@intel.com>2020-02-24 15:14:22 +0530
committerPatrick Georgi <pgeorgi@google.com>2020-02-26 17:08:50 +0000
commit1bfd56cb2509c239ed683667e61789a4ba5d3079 (patch)
tree1d072206c5929746f06da34392660cce242d6935
parentfdba0cd6af05f9317dbd19956d644ce01e37a547 (diff)
downloadcoreboot-1bfd56cb2509c239ed683667e61789a4ba5d3079.tar.xz
soc/intel/tigerlake: Integrate Legacy 8254 timer support
This patch overrides required FSP-S UPDs to enable 8254 timer support for TGL if CONFIG_USE_LEGACY_8254_TIMER is selected. TEST=Required to boot TianoCore payload. Change-Id: Iaeff5c4b92691ed6ba7b71541ed4f947d5d299a8 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
-rw-r--r--src/soc/intel/tigerlake/fsp_params_tgl.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c
index 305748e8f3..d22cde021c 100644
--- a/src/soc/intel/tigerlake/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/fsp_params_tgl.c
@@ -135,6 +135,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
sizeof(params->SataPortsDevSlp));
}
+ /* Legacy 8254 timer support */
+ params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
+ params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER;
+
mainboard_silicon_init_params(params);
}