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authorTristan Shieh <tristan.shieh@mediatek.com>2019-01-28 13:28:14 +0800
committerPatrick Georgi <pgeorgi@google.com>2019-01-29 12:30:47 +0000
commit1e504f7811273b5a6a94bb82b94031112069dd56 (patch)
tree1f4c11d7d8a8f869aa0cefef6811d72956a19e9b
parente6a03e0b1b75b8470c992346376e098187b14f12 (diff)
downloadcoreboot-1e504f7811273b5a6a94bb82b94031112069dd56.tar.xz
google/kukui: Implement HW reset function
Asserting GPIO PERIPHERAL_EN8 will send a signal to EC to trigger a HW reset for SoC and H1. BUG=b:80501386 BRANCH=none TEST=emerge-kukui coreboot; manually verified the do_board_reset() on Kukui P1 Change-Id: I9afad84af2031a766bc08fc76c8b5f55588c453a Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/c/31118 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/kukui/Kconfig1
-rw-r--r--src/mainboard/google/kukui/Makefile.inc4
-rw-r--r--src/mainboard/google/kukui/gpio.h1
-rw-r--r--src/mainboard/google/kukui/reset.c24
4 files changed, 29 insertions, 1 deletions
diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig
index 902fa38acb..7635e5fcf7 100644
--- a/src/mainboard/google/kukui/Kconfig
+++ b/src/mainboard/google/kukui/Kconfig
@@ -37,7 +37,6 @@ config BOARD_SPECIFIC_OPTIONS
select EC_GOOGLE_CHROMEEC_SPI
select MAINBOARD_HAS_SPI_TPM_CR50 if VBOOT
select MAINBOARD_HAS_TPM2 if VBOOT
- select MISSING_BOARD_RESET
config MAINBOARD_DIR
string
diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc
index acd2c45417..9f8c313e74 100644
--- a/src/mainboard/google/kukui/Makefile.inc
+++ b/src/mainboard/google/kukui/Makefile.inc
@@ -4,15 +4,18 @@ bootblock-y += boardid.c
bootblock-y += bootblock.c
bootblock-y += chromeos.c
bootblock-y += memlayout.ld
+bootblock-y += reset.c
decompressor-y += memlayout.ld
verstage-y += chromeos.c
+verstage-y += reset.c
verstage-y += verstage.c
verstage-y += memlayout.ld
romstage-y += boardid.c
romstage-y += chromeos.c
romstage-y += memlayout.ld
+romstage-y += reset.c
romstage-y += romstage.c
romstage-y += sdram_configs.c
@@ -20,3 +23,4 @@ ramstage-y += boardid.c
ramstage-y += chromeos.c
ramstage-y += mainboard.c
ramstage-y += memlayout.ld
+ramstage-y += reset.c
diff --git a/src/mainboard/google/kukui/gpio.h b/src/mainboard/google/kukui/gpio.h
index 20a50a6923..024b0d79db 100644
--- a/src/mainboard/google/kukui/gpio.h
+++ b/src/mainboard/google/kukui/gpio.h
@@ -21,6 +21,7 @@
#define EC_IRQ GPIO(PERIPHERAL_EN1)
#define EC_IN_RW GPIO(PERIPHERAL_EN14)
#define CR50_IRQ GPIO(PERIPHERAL_EN3)
+#define GPIO_RESET GPIO(PERIPHERAL_EN8)
void setup_chromeos_gpios(void);
diff --git a/src/mainboard/google/kukui/reset.c b/src/mainboard/google/kukui/reset.c
new file mode 100644
index 0000000000..609ecb4c1a
--- /dev/null
+++ b/src/mainboard/google/kukui/reset.c
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <gpio.h>
+#include <reset.h>
+
+#include "gpio.h"
+
+void do_board_reset(void)
+{
+ gpio_output(GPIO_RESET, 1);
+}