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authorEugene D. Myers <edmyers@tycho.nsa.gov>2019-07-02 14:06:46 -0400
committerron minnich <rminnich@gmail.com>2019-12-18 00:33:30 +0000
commit297b6b862a724de70abf33f681f63b6a3d84c24b (patch)
treeb40b6b473ffb212c612118dd219b4446e40a26f6
parent7a1b60b694f397e4a7c3ddd8c7242f8c312212f8 (diff)
downloadcoreboot-297b6b862a724de70abf33f681f63b6a3d84c24b.tar.xz
include/cpu/x86: Add STM Support
Addtions to include/cpu/x86 include for STM support. Change-Id: I2b8e68b2928aefc7996b6a9560c52f71c7c0e1d0 Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: ron minnich <rminnich@gmail.com>
-rw-r--r--src/include/cpu/x86/msr.h6
-rw-r--r--src/include/cpu/x86/smm.h3
2 files changed, 9 insertions, 0 deletions
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index 2710e7f1fc..0da8b564fa 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -30,6 +30,10 @@
#define IA32_BIOS_SIGN_ID 0x8b
#define IA32_MPERF 0xe7
#define IA32_APERF 0xe8
+/* STM */
+#define IA32_SMM_MONITOR_CTL_MSR 0x9B
+#define SMBASE_RO_MSR 0x98
+#define IA32_SMM_MONITOR_VALID (1<<0)
#define IA32_MCG_CAP 0x179
#define MCG_CTL_P (1 << 3)
#define MCA_BANKS_MASK 0xff
@@ -48,6 +52,8 @@
#define IA32_PAT 0x277
#define IA32_MC0_CTL 0x400
#define IA32_MC0_STATUS 0x401
+#define IA32_VMX_BASIC_MSR 0x480
+#define IA32_VMX_MISC_MSR 0x485
#define MCA_STATUS_HI_VAL (1UL << (63 - 32))
#define MCA_STATUS_HI_OVERFLOW (1UL << (62 - 32))
#define MCA_STATUS_HI_UC (1UL << (61 - 32))
diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index cf107b121a..9efe2e04eb 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -64,6 +64,9 @@ extern unsigned char _binary_smm_end[];
struct smm_runtime {
u32 smbase;
u32 save_state_size;
+ u32 num_cpus;
+ /* STM's 32bit entry into SMI handler */
+ u32 start32_offset;
/* The apic_id_to_cpu provides a mapping from APIC id to CPU number.
* The CPU number is indicated by the index into the array by matching
* the default APIC id and value at the index. The stub loader