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authorZheng Bao <zheng.bao@amd.com>2010-12-06 08:19:38 +0000
committerZheng Bao <Zheng.Bao@amd.com>2010-12-06 08:19:38 +0000
commit29cb06abca665954e910f91397957ec93c627e86 (patch)
treefcce2b56b7e0de9c1b8f71e86d8659ceb8c00228
parenta8c8490c114f97462a3060ce77777ea546d0bbc4 (diff)
downloadcoreboot-29cb06abca665954e910f91397957ec93c627e86.tar.xz
Before lane reversal,
De-asserts STRAP_BIF_all_valid for PCIE-GFX core. After lane reversal, Asserts STRAP_BIF_all_valid for PCIE-GFX core. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: QingPei Wang <wangqingpei@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6142 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
-rw-r--r--src/southbridge/amd/rs780/rs780_gfx.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/southbridge/amd/rs780/rs780_gfx.c b/src/southbridge/amd/rs780/rs780_gfx.c
index 18836675e0..1763c36047 100644
--- a/src/southbridge/amd/rs780/rs780_gfx.c
+++ b/src/southbridge/amd/rs780/rs780_gfx.c
@@ -1302,8 +1302,10 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
if(is_dev3_present()){
/* step 1, lane reversal (only need if CMOS option is enabled) */
if (cfg->gfx_lane_reversal) {
+ set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3);
+ set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31);
}
printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
/* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */
@@ -1317,10 +1319,11 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
}else{
if (cfg->gfx_lane_reversal) {
+ set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
+ set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 0 << 31);
}
printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
- printk(BIOS_DEBUG, "rs780_gfx_init step2.\n");
if((dev->path.pci.devfn >> 3) == 2)
single_port_configuration(nb_dev, dev);