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authorMatt DeVillier <matt.devillier@gmail.com>2017-05-25 15:53:29 -0500
committerMartin Roth <martinroth@google.com>2017-06-16 16:04:31 +0200
commit2ae2742065a359ce6a45f3b9da7424e8e374b6fa (patch)
tree283167b7242a81958e2351bf0b1678d7a00e9321
parent2fa66164d86c56f8aee30636a522cf560a2f5882 (diff)
downloadcoreboot-2ae2742065a359ce6a45f3b9da7424e8e374b6fa.tar.xz
purism/librem13v2: Clean up devicetree
- remove unused I2C, serialIO defs - set PL2 override, VR mailbox cmd based on SKL-U ref board, as values copied from google/chell are for SKL-Y Change-Id: I3a138c28d0322df6cb41ec1a845ae31602cb69a7 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
-rw-r--r--src/mainboard/purism/librem13v2/devicetree.cb27
1 files changed, 4 insertions, 23 deletions
diff --git a/src/mainboard/purism/librem13v2/devicetree.cb b/src/mainboard/purism/librem13v2/devicetree.cb
index 0defea089e..f345c09f38 100644
--- a/src/mainboard/purism/librem13v2/devicetree.cb
+++ b/src/mainboard/purism/librem13v2/devicetree.cb
@@ -165,30 +165,11 @@ chip soc/intel/skylake
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (right)
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
- register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
-
- # Must leave UART0 enabled or SD/eMMC will not work as PCI
- register "SerialIoDevMode" = "{
- [PchSerialIoIndexI2C0] = PchSerialIoPci,
- [PchSerialIoIndexI2C1] = PchSerialIoPci,
- [PchSerialIoIndexI2C2] = PchSerialIoDisabled,
- [PchSerialIoIndexI2C3] = PchSerialIoDisabled,
- [PchSerialIoIndexI2C4] = PchSerialIoPci,
- [PchSerialIoIndexI2C5] = PchSerialIoDisabled,
- [PchSerialIoIndexSpi0] = PchSerialIoDisabled,
- [PchSerialIoIndexSpi1] = PchSerialIoDisabled,
- [PchSerialIoIndexUart0] = PchSerialIoPci,
- [PchSerialIoIndexUart1] = PchSerialIoDisabled,
- [PchSerialIoIndexUart2] = PchSerialIoSkipInit,
- }"
-
- # PL2 override 15W
- register "tdp_pl2_override" = "15"
-
- register "tcc_offset" = "10" # TCC of 90C
+ # PL2 override 25W
+ register "tdp_pl2_override" = "25"
- # Send an extra VR mailbox command for the supported MPS IMVP8 model
- register "SendVrMbxCmd" = "1"
+ # Send an extra VR mailbox command for the PS4 exit issue
+ register "SendVrMbxCmd" = "2"
device cpu_cluster 0 on
device lapic 0 on end