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author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-24 19:05:47 +0100 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-26 11:43:04 +0000 |
commit | 2ed6848ea3530beb234a3b9d5c843a54688d1d3c (patch) | |
tree | f1ad8aa91516ecd18bbcee3568f864f5b9f3780f | |
parent | 8d82109c08163fa82263b35e9aa0a270a795a5f8 (diff) | |
download | coreboot-2ed6848ea3530beb234a3b9d5c843a54688d1d3c.tar.xz |
soc/amd/exit_car.S: Drop redundant enabling cache
This is already done in arch/x86/exit_car.S
Change-Id: Ie954aa11d5e76aaa3e2185ba552aafe8d075feb6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
-rw-r--r-- | src/soc/amd/common/block/cpu/car/exit_car.S | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/soc/amd/common/block/cpu/car/exit_car.S b/src/soc/amd/common/block/cpu/car/exit_car.S index f9d056e599..16880e71a5 100644 --- a/src/soc/amd/common/block/cpu/car/exit_car.S +++ b/src/soc/amd/common/block/cpu/car/exit_car.S @@ -29,9 +29,4 @@ chipset_teardown_car: AMD_DISABLE_STACK - /* enable cache */ - movl %cr0, %eax - andl $(~(CR0_CD | CR0_NW)), %eax - movl %eax, %cr0 - jmp *%esp |