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authorPatrick Rudolph <patrick.rudolph@9elements.com>2020-08-06 07:54:37 +0200
committerPatrick Rudolph <siro@das-labor.org>2020-08-12 05:30:28 +0000
commit3299b2ded5327cd4a40e68554a8c2fd227355ada (patch)
tree7901e1aa42059066f59dfa843574777a7274a62d
parent988da3142df49908ca8f344102955a24a540028b (diff)
downloadcoreboot-3299b2ded5327cd4a40e68554a8c2fd227355ada.tar.xz
soc/intel/tigerlake: Add IRQs for LPSS uart
Values are taken from pci_irqs.asl. The common code will make use of those defines to generate ACPI SSDT code for LPSS uarts operating in "ACPI mode". Change-Id: I5ef93493965834cda30d70918e65de3129e547b7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44260 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/intel/tigerlake/include/soc/irq.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/include/soc/irq.h b/src/soc/intel/tigerlake/include/soc/irq.h
index ad70290148..f95f9f672c 100644
--- a/src/soc/intel/tigerlake/include/soc/irq.h
+++ b/src/soc/intel/tigerlake/include/soc/irq.h
@@ -9,4 +9,8 @@
#define PCH_IRQ10 10
#define PCH_IRQ11 11
+#define LPSS_UART0_IRQ 16
+#define LPSS_UART1_IRQ 17
+#define LPSS_UART2_IRQ 33
+
#endif /* _SOC_IRQ_H_ */