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authorArthur Heymans <arthur@aheymans.xyz>2017-03-01 20:10:55 +0100
committerMartin Roth <martinroth@google.com>2017-09-06 04:38:55 +0000
commit3397aa1fd469335e99befec2fbf93d505f58d70c (patch)
tree3d9d00283599c8db2372112ce2e6f011dd307512
parent57443690254d86558c38682f65e85ae69e3148bc (diff)
downloadcoreboot-3397aa1fd469335e99befec2fbf93d505f58d70c.tar.xz
device/dram/ddr2: Add a function to normalize tCLK
Also make most significant bit function accessible outside the scope of this file. Change-Id: I3ab39d38a243edddfde8f70ebd23f79ff774e90e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
-rw-r--r--src/device/dram/ddr2.c33
-rw-r--r--src/include/device/dram/ddr2.h3
2 files changed, 28 insertions, 8 deletions
diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c
index 249399ff14..326b1410fa 100644
--- a/src/device/dram/ddr2.c
+++ b/src/device/dram/ddr2.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2017 Patrick Rudolph <siro@das-labor.org>
+ * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -23,6 +24,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/dram/ddr2.h>
+#include <lib.h>
#include <string.h>
/*==============================================================================
@@ -100,14 +102,9 @@ u32 spd_decode_eeprom_size_ddr2(u8 byte1)
*
* Returns the index fof MSB set.
*/
-static u8 spd_get_msbs(u8 c)
+u8 spd_get_msbs(u8 c)
{
- int i;
- for (i = 7; i >= 0; i--)
- if (c & (1 << i))
- return i;
-
- return 0;
+ return log2(c);
}
/**
@@ -629,3 +626,25 @@ void dram_print_spd_ddr2(const struct dimm_attr_st *dimm)
print_us(" tPLL : ", dimm->tPLL);
print_us(" tRR : ", dimm->tRR);
}
+
+void normalize_tck(u32 *tclk)
+{
+ if (*tclk <= TCK_800MHZ) {
+ *tclk = TCK_800MHZ;
+ } else if (*tclk <= TCK_666MHZ) {
+ *tclk = TCK_666MHZ;
+ } else if (*tclk <= TCK_533MHZ) {
+ *tclk = TCK_533MHZ;
+ } else if (*tclk <= TCK_400MHZ) {
+ *tclk = TCK_400MHZ;
+ } else if (*tclk <= TCK_333MHZ) {
+ *tclk = TCK_333MHZ;
+ } else if (*tclk <= TCK_266MHZ) {
+ *tclk = TCK_266MHZ;
+ } else if (*tclk <= TCK_200MHZ) {
+ *tclk = TCK_200MHZ;
+ } else {
+ *tclk = 0;
+ printk(BIOS_ERR, "Too slow common tCLK found\n");
+ }
+}
diff --git a/src/include/device/dram/ddr2.h b/src/include/device/dram/ddr2.h
index 8ea80b986a..ea9b3ba535 100644
--- a/src/include/device/dram/ddr2.h
+++ b/src/include/device/dram/ddr2.h
@@ -213,6 +213,7 @@ u32 spd_decode_spd_size_ddr2(u8 byte0);
u32 spd_decode_eeprom_size_ddr2(u8 byte1);
int spd_decode_ddr2(struct dimm_attr_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2]);
void dram_print_spd_ddr2(const struct dimm_attr_st *dimm);
-
+void normalize_tck(u32 *tclk);
+u8 spd_get_msbs(u8 c);
#endif /* DEVICE_DRAM_DDR2L_H */