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authorDuncan Laurie <dlaurie@chromium.org>2017-01-18 14:31:59 -0800
committerMartin Roth <martinroth@google.com>2017-01-20 17:18:48 +0100
commit3c78eae369ff3f96dbc901ca6c258b3e5fea847e (patch)
treec72275c54825a05d981df0f77c0a6b404812bed3
parentcdb93a592274f4e8f423b5d27ecf25374e7dcd15 (diff)
downloadcoreboot-3c78eae369ff3f96dbc901ca6c258b3e5fea847e.tar.xz
google/eve: Adjust DPTF parameters
- Remove the 0mA entry for the charger performance table - Slightly raise the passive limit for TSR2/TSR3 to 55C BUG=chrome-os-partner:58666 TEST=manual testing on P1 system Change-Id: I75c66afe04afbbdb64a45833eb938e57ff21b392 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18172 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r--src/mainboard/google/eve/acpi/dptf.asl5
1 files changed, 2 insertions, 3 deletions
diff --git a/src/mainboard/google/eve/acpi/dptf.asl b/src/mainboard/google/eve/acpi/dptf.asl
index 95985f6a41..eaacb46f43 100644
--- a/src/mainboard/google/eve/acpi/dptf.asl
+++ b/src/mainboard/google/eve/acpi/dptf.asl
@@ -29,12 +29,12 @@
#define DPTF_TSR2_SENSOR_ID 3
#define DPTF_TSR2_SENSOR_NAME "DRAM"
-#define DPTF_TSR2_PASSIVE 50
+#define DPTF_TSR2_PASSIVE 55
#define DPTF_TSR2_CRITICAL 75
#define DPTF_TSR3_SENSOR_ID 4
#define DPTF_TSR3_SENSOR_NAME "eMMC"
-#define DPTF_TSR3_PASSIVE 50
+#define DPTF_TSR3_PASSIVE 55
#define DPTF_TSR3_CRITICAL 75
#undef DPTF_ENABLE_FAN_CONTROL
@@ -46,7 +46,6 @@ Name (CHPS, Package () {
Package () { 0, 0, 0, 0, 24, 0x800, "mA", 0 }, /* 2000mA */
Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1000mA */
Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 500mA */
- Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0mA */
})
Name (DTRT, Package () {